Simulation Results

Simulation Results: i2c

03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
85.15 %

code
78.29 %

assert
95.98 %

func
81.18 %

line
96.35 %

branch
92.12 %

cond
85.08 %

toggle
73.87 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	27.660s	3581.367us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	17.410s	2780.868us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.080s	40.922us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.970s	29.082us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.600s	649.283us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.020s	31.713us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.030s	29.039us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.970s	29.082us	1	1	100.00
	i2c_csr_aliasing	1.020s	31.713us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	1.830s	168.215us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	436.420s	30583.939us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	760.850s	12186.085us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.980s	64.456us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	75.760s	3725.113us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	70.820s	2475.295us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.450s	294.235us	1	1	100.00
	i2c_host_fifo_fmt_empty	6.860s	4517.495us	1	1	100.00
	i2c_host_fifo_reset_rx	7.850s	390.167us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	79.730s	8519.851us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	40.220s	3960.763us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.650s	512.866us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.930s	2179.150us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	66.300s	45715.831us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	6.730s	932.292us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	36.000s	8711.890us	1	1	100.00
	i2c_target_intr_smoke	4.300s	545.128us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.540s	1045.700us	1	1	100.00
	i2c_target_fifo_reset_tx	1.480s	221.367us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	31.440s	22860.599us	1	1	100.00
	i2c_target_stress_rd	36.000s	8711.890us	1	1	100.00
	i2c_target_intr_stress_wr	1.720s	886.187us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	6.980s	13493.276us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	19.800s	3149.715us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.110s	3758.508us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	2.050s	721.191us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.450s	157.102us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.460s	561.917us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	760.850s	12186.085us	1	1	100.00
	i2c_host_perf_precise	2.630s	540.767us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	40.220s	3960.763us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	8.920s	651.712us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	3.220s	604.683us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.890s	548.718us	1	1	100.00
	i2c_target_nack_txstretch	1.500s	309.905us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.640s	253.456us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.690s	1063.578us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.980s	17.729us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.960s	173.042us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.680s	427.891us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.680s	427.891us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.080s	40.922us	1	1	100.00
	i2c_csr_rw	0.970s	29.082us	1	1	100.00
	i2c_csr_aliasing	1.020s	31.713us	1	1	100.00
	i2c_same_csr_outstanding	1.160s	272.162us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.080s	40.922us	1	1	100.00
	i2c_csr_rw	0.970s	29.082us	1	1	100.00
	i2c_csr_aliasing	1.020s	31.713us	1	1	100.00
	i2c_same_csr_outstanding	1.160s	272.162us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.720s	346.882us	1	1	100.00
	i2c_sec_cm	1.380s	72.501us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.720s	346.882us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	7.250s	576.848us	1
target_error_intr				1
	i2c_target_unexp_stop	1.170s	182.726us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	1.400s	274.014us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_stress_all	107605183565349533600162797547305041309937022810046904314251347744247754310529	171	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @3545732
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	57798844227631509017186285023283401242165850535120381442584874465964632707010	90	UVM_INFO @ 2179150383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	29934587562719256861386326382998623931303484944818372429897909343771691291613	84	UVM_INFO @ 182726405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	79323866416311272405566696838388265949502330053888781673254328523581890172127	93	UVM_INFO @ 576847731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_target_stress_all_with_rand_reset	32179287304243163584148869428022772520320511534087821120674325134127670295460	91	UVM_INFO @ 274013824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	50987753358739158736682646506046729699903591626435806711930739226150961325139	84	UVM_INFO @ 309905497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---