Simulation Results: keymgr_dpe/earlgrey

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 65.18 %
  • code
  • 82.68 %
  • assert
  • 97.67 %
  • func
  • 15.19 %
  • line
  • 97.60 %
  • branch
  • 93.77 %
  • cond
  • 86.84 %
  • toggle
  • 59.49 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 13.740s 1385.412us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.030s 19.286us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 1.000s 61.252us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 7.310s 512.691us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 1.340s 104.922us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.640s 95.897us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 1.000s 61.252us 1 1 100.00
keymgr_dpe_csr_aliasing 1.340s 104.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.980s 55.509us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 1.010s 35.665us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 3.660s 282.926us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 3.660s 282.926us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.030s 19.286us 1 1 100.00
keymgr_dpe_csr_rw 1.000s 61.252us 1 1 100.00
keymgr_dpe_csr_aliasing 1.340s 104.922us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.910s 118.762us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 1.030s 19.286us 1 1 100.00
keymgr_dpe_csr_rw 1.000s 61.252us 1 1 100.00
keymgr_dpe_csr_aliasing 1.340s 104.922us 1 1 100.00
keymgr_dpe_same_csr_outstanding 1.910s 118.762us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 12.380s 746.531us 1 1 100.00
keymgr_dpe_tl_intg_err 3.460s 138.251us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.970s 52.355us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.970s 52.355us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.970s 52.355us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.970s 52.355us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 3.260s 192.632us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 12.380s 746.531us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 12.380s 746.531us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_dst_sel.q < NumInstHwSlot)' 2 test runs
keymgr_dpe_shadow_reg_errors 1131169661818113273553415741458309680468230076087853595007864989796641191513 83
UVM_ERROR @ 52355359 ps: (keymgr_dpe.sv:321) [ASSERT FAILED] DstSelInRange_A
UVM_INFO @ 52355359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_dpe_shadow_reg_errors_with_csr_rw 37055111768560962985132718889727057206087484282314461077518055778984808748547 83
UVM_ERROR @ 192632282 ps: (keymgr_dpe.sv:321) [ASSERT FAILED] DstSelInRange_A
UVM_INFO @ 192632282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---