Simulation Results: lc_ctrl/volatile_unlock_disabled

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 89.41 %
  • code
  • 83.06 %
  • assert
  • 94.13 %
  • func
  • 91.04 %
  • line
  • 97.15 %
  • branch
  • 93.47 %
  • cond
  • 79.52 %
  • toggle
  • 83.46 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
90.00%
V2S
90.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.250s 51.283us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.070s 46.287us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.050s 49.160us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.550s 64.430us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 34.257us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.300s 67.217us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.050s 49.160us 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 34.257us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.530s 67.278us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.240s 1226.366us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.080s 20.474us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.210s 85.087us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.850s 283.300us 1 1 100.00
lc_errors 0 1 0.00
lc_ctrl_errors 4.350s 188.481us 0 1 0.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 9.850s 283.300us 1 1 100.00
lc_ctrl_prog_failure 2.210s 85.087us 1 1 100.00
lc_ctrl_errors 4.350s 188.481us 0 1 0.00
lc_ctrl_security_escalation 5.150s 811.422us 1 1 100.00
lc_ctrl_jtag_state_failure 21.850s 4383.882us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.020s 328.783us 1 1 100.00
lc_ctrl_jtag_errors 24.530s 1752.189us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 2.540s 203.713us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.350s 1644.299us 0 1 0.00
lc_ctrl_jtag_prog_failure 7.020s 328.783us 1 1 100.00
lc_ctrl_jtag_errors 24.530s 1752.189us 1 1 100.00
lc_ctrl_jtag_access 11.060s 804.003us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.190s 11391.972us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.610s 206.947us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.410s 34.986us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.110s 1270.390us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.120s 697.849us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.480s 67.683us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.950s 60.358us 1 1 100.00
lc_ctrl_jtag_alert_test 1.660s 315.657us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.700s 1540.764us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.190s 15.323us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 173.700s 34626.110us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.230s 20.164us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.890s 174.025us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.890s 174.025us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.070s 46.287us 1 1 100.00
lc_ctrl_csr_rw 1.050s 49.160us 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 34.257us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.790s 46.603us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.070s 46.287us 1 1 100.00
lc_ctrl_csr_rw 1.050s 49.160us 1 1 100.00
lc_ctrl_csr_aliasing 1.330s 34.257us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.790s 46.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.330s 919.147us 1 1 100.00
lc_ctrl_tl_intg_err 3.100s 728.546us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.100s 728.546us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.240s 1226.366us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.850s 283.300us 1 1 100.00
lc_ctrl_sec_cm 6.330s 919.147us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.850s 283.300us 1 1 100.00
lc_ctrl_sec_cm 6.330s 919.147us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.850s 283.300us 1 1 100.00
lc_ctrl_sec_cm 6.330s 919.147us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.850s 283.300us 1 1 100.00
lc_ctrl_sec_cm 6.330s 919.147us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.850s 283.300us 1 1 100.00
lc_ctrl_sec_cm 6.330s 919.147us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.850s 283.300us 1 1 100.00
lc_ctrl_sec_cm 6.330s 919.147us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.850s 283.300us 1 1 100.00
lc_ctrl_sec_cm 6.330s 919.147us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.850s 283.300us 1 1 100.00
lc_ctrl_sec_cm 6.330s 919.147us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.150s 811.422us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 3.530s 67.278us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.350s 1644.299us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.780s 1067.533us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.780s 1067.533us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.870s 518.334us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.450s 2484.199us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.450s 2484.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 7.260s 2754.566us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_post_trans 45385528687150562368815913117068481703247292525434931112606238297881519772669 574
UVM_INFO @ 1644299343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 13858423138017206298168239977388027818764740698664211220475335698255117075904 4526
UVM_INFO @ 34626110044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_errors 65713592785480482634927566854217133367063415356173968405952961017129604234889 1779
UVM_INFO @ 188481428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 68180111211146550199441297255440025307438405337522946167640432116004013449080 216
UVM_INFO @ 2754565961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---