Simulation Results: lc_ctrl/volatile_unlock_enabled

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 90.43 %
  • code
  • 83.55 %
  • assert
  • 94.55 %
  • func
  • 93.19 %
  • line
  • 97.00 %
  • branch
  • 93.14 %
  • cond
  • 79.28 %
  • toggle
  • 82.90 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.180s 34.925us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.110s 17.090us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.950s 45.465us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.340s 137.793us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 32.747us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.290s 80.156us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.950s 45.465us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 32.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.340s 93.710us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.090s 187.804us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.090s 13.234us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.390s 69.553us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.040s 692.224us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.770s 1725.146us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 9.040s 692.224us 1 1 100.00
lc_ctrl_prog_failure 2.390s 69.553us 1 1 100.00
lc_ctrl_errors 5.770s 1725.146us 1 1 100.00
lc_ctrl_security_escalation 5.350s 1206.875us 1 1 100.00
lc_ctrl_jtag_state_failure 15.090s 4851.089us 0 1 0.00
lc_ctrl_jtag_prog_failure 2.710s 629.277us 1 1 100.00
lc_ctrl_jtag_errors 10.240s 4602.939us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 2.030s 89.003us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.630s 622.850us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.710s 629.277us 1 1 100.00
lc_ctrl_jtag_errors 10.240s 4602.939us 0 1 0.00
lc_ctrl_jtag_access 9.220s 2310.582us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.110s 4574.925us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.740s 143.172us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.820s 311.143us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.240s 1341.593us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 1.920s 318.887us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.710s 355.744us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.840s 1137.027us 1 1 100.00
lc_ctrl_jtag_alert_test 0.980s 45.020us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 21.490s 2386.232us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.920s 12.780us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 12.790s 722.831us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.120s 31.770us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.500s 251.831us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.500s 251.831us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.110s 17.090us 1 1 100.00
lc_ctrl_csr_rw 0.950s 45.465us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 32.747us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.220s 58.837us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.110s 17.090us 1 1 100.00
lc_ctrl_csr_rw 0.950s 45.465us 1 1 100.00
lc_ctrl_csr_aliasing 1.070s 32.747us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.220s 58.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.090s 259.762us 1 1 100.00
lc_ctrl_tl_intg_err 1.810s 454.029us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.810s 454.029us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.090s 187.804us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.040s 692.224us 1 1 100.00
lc_ctrl_sec_cm 6.090s 259.762us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.040s 692.224us 1 1 100.00
lc_ctrl_sec_cm 6.090s 259.762us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.040s 692.224us 1 1 100.00
lc_ctrl_sec_cm 6.090s 259.762us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.040s 692.224us 1 1 100.00
lc_ctrl_sec_cm 6.090s 259.762us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.040s 692.224us 1 1 100.00
lc_ctrl_sec_cm 6.090s 259.762us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.040s 692.224us 1 1 100.00
lc_ctrl_sec_cm 6.090s 259.762us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.040s 692.224us 1 1 100.00
lc_ctrl_sec_cm 6.090s 259.762us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.040s 692.224us 1 1 100.00
lc_ctrl_sec_cm 6.090s 259.762us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.350s 1206.875us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.340s 93.710us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.630s 622.850us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.200s 433.546us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.200s 433.546us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.210s 279.764us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.290s 259.484us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.290s 259.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 4.260s 1012.059us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_errors 12950832187305935028418304159265492477529422821534500723208002980217337861927 1383
UVM_INFO @ 4602938551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60459249409988665873351218932412201582698298041399111689642175607902615735933 214
UVM_INFO @ 1012058824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 99449011427587820487741116328996883994866366515800509378197420407097203300506 2246
UVM_INFO @ 4851088977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---