Simulation Results: otp_ctrl

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 79.31 %
  • code
  • 76.89 %
  • assert
  • 94.44 %
  • func
  • 66.59 %
  • line
  • 88.49 %
  • branch
  • 83.18 %
  • cond
  • 90.30 %
  • toggle
  • 77.67 %
  • FSM
  • 44.79 %
Validation stages
V1
100.00%
V2
90.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.490s 56.660us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 14.690s 8302.513us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.550s 76.722us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.190s 91.586us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 9.740s 1491.209us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 1.690s 157.198us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.990s 107.794us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.190s 91.586us 1 1 100.00
otp_ctrl_csr_aliasing 1.690s 157.198us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.660s 38.449us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.550s 473.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 17.780s 1874.092us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.590s 173.279us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 7.600s 1673.503us 1 1 100.00
otp_ctrl_check_fail 3.040s 87.746us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.910s 147.578us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 25.280s 5602.694us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 14.520s 4920.112us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 6.320s 846.911us 1 1 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 14.210s 376.774us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 9.420s 3020.136us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 16.100s 1368.079us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 39.960s 18158.435us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.780s 70.667us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.950s 123.328us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.800s 159.487us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.800s 159.487us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.550s 76.722us 1 1 100.00
otp_ctrl_csr_rw 2.190s 91.586us 1 1 100.00
otp_ctrl_csr_aliasing 1.690s 157.198us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.880s 54.191us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.550s 76.722us 1 1 100.00
otp_ctrl_csr_rw 2.190s 91.586us 1 1 100.00
otp_ctrl_csr_aliasing 1.690s 157.198us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.880s 54.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
otp_ctrl_tl_intg_err 15.990s 1931.740us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 15.990s 1931.740us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 14.690s 8302.513us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 14.690s 8302.513us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
otp_ctrl_macro_errs 9.420s 3020.136us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
otp_ctrl_macro_errs 9.420s 3020.136us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.090s 839.353us 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.590s 173.279us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 3.040s 87.746us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 25.280s 5602.694us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 25.280s 5602.694us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 25.280s 5602.694us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 25.280s 5602.694us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 25.280s 5602.694us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 14.690s 8302.513us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 25.280s 5602.694us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 14.690s 8302.513us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 147.260s 20337.794us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.910s 147.578us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 14.690s 8302.513us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 14.690s 8302.513us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 9.420s 3020.136us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 24.820s 8591.664us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 99.080s 39263.678us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 54526764579247656674954933375678801832606095289932278157848454557942115978538 2255
UVM_INFO @ 87746120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_macro_error has unexpected timeout error 1 test run
otp_ctrl_macro_errs 98934755180015720376986274436262006864329120557976129154870651675115243693589 4121
UVM_INFO @ 3020136038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
otp_ctrl_stress_all_with_rand_reset 3688266204423162755790304836232605415313129346704039209458867802443563252680 15337
UVM_INFO @ 39263678013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---