Simulation Results: pwrmgr

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.59 %
  • code
  • 94.38 %
  • assert
  • 96.34 %
  • func
  • 96.05 %
  • line
  • 98.93 %
  • branch
  • 95.62 %
  • cond
  • 93.35 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
83.33%
V2
93.33%
V2S
72.73%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.850s 37.760us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.810s 44.387us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.650s 59.856us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.610s 100.036us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.820s 89.681us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
pwrmgr_csr_mem_rw_with_rand_reset 3600.034s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.650s 59.856us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 89.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.940s 383.040us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.940s 383.040us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.910s 68.231us 1 1 100.00
pwrmgr_lowpower_invalid 0.820s 44.038us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 1.020s 310.002us 1 1 100.00
pwrmgr_reset_invalid 0.910s 125.932us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 1.020s 310.002us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.900s 79.512us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 1.170s 309.614us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.250s 124.787us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 10800.036s 0.000us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.710s 19.227us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.130s 144.929us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.130s 144.929us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.810s 44.387us 1 1 100.00
pwrmgr_csr_rw 0.650s 59.856us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 89.681us 1 1 100.00
pwrmgr_same_csr_outstanding 1.030s 47.758us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.810s 44.387us 1 1 100.00
pwrmgr_csr_rw 0.650s 59.856us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 89.681us 1 1 100.00
pwrmgr_same_csr_outstanding 1.030s 47.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 3600.024s 0.000us 0 1 0.00
pwrmgr_sec_cm 3600.030s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 3600.030s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 3600.030s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 3600.024s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.730s 822.044us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.900s 79.512us 1 1 100.00
pwrmgr_repeat_wakeup_reset 2.330s 959.195us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.160s 112.862us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.720s 40.093us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 3600.030s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 3600.030s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 3600.030s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.720s 59.539us 1 1 100.00
sec_cm_main_pd_rst_local_esc 0 1 0.00
pwrmgr_glitch 3600.027s 0.000us 0 1 0.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.820s 28.229us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.650s 59.856us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.650s 59.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.790s 374.735us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 3600.033s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 6 test runs
pwrmgr_glitch 104517105104728085089012435466453429085818699413015500153086072851887161044875 None
pwrmgr_tl_intg_err 82121860173181337536636215847806635595137329224148295004466754359310590226378 None
pwrmgr_sec_cm 51122385500697546196118184215892141773865214540819184295905326798611519088613 None
pwrmgr_stress_all_with_rand_reset 60511004379657425976607061013495408871523720529228408506430189921821741168782 None
pwrmgr_stress_all 37955207068026481234028877141500395159491427413608148570398390445567107311271 None
pwrmgr_csr_mem_rw_with_rand_reset 33599037638037619771561057018402484278894814056083000277314822772545243811821 None