Simulation Results: rom_ctrl/192kb

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 94.20 %
  • code
  • 95.28 %
  • assert
  • 96.66 %
  • func
  • 90.65 %
  • line
  • 98.95 %
  • branch
  • 98.56 %
  • cond
  • 97.33 %
  • toggle
  • 94.90 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 19.990s 4151.350us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 21.730s 77.511us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 12.420s 85.642us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 13.020s 320.258us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 11.310s 90.226us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 12.100s 118.444us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 12.420s 85.642us 1 1 100.00
rom_ctrl_csr_aliasing 11.310s 90.226us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 11.920s 77.070us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 11.590s 49.283us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 18.400s 1006.679us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 57.300s 8013.736us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 22.660s 59.814us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 12.320s 74.204us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 20.790s 1419.227us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 20.790s 1419.227us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 21.730s 77.511us 1 1 100.00
rom_ctrl_csr_rw 12.420s 85.642us 1 1 100.00
rom_ctrl_csr_aliasing 11.310s 90.226us 1 1 100.00
rom_ctrl_same_csr_outstanding 22.280s 59.077us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 21.730s 77.511us 1 1 100.00
rom_ctrl_csr_rw 12.420s 85.642us 1 1 100.00
rom_ctrl_csr_aliasing 11.310s 90.226us 1 1 100.00
rom_ctrl_same_csr_outstanding 22.280s 59.077us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 390.490s 13951.156us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.820s 172.879us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 868.060s 299.768us 1 1 100.00
rom_ctrl_tl_intg_err 194.580s 268.354us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 868.060s 299.768us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 868.060s 299.768us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 390.490s 13951.156us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 390.490s 13951.156us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 390.490s 13951.156us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 390.490s 13951.156us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 390.490s 13951.156us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 868.060s 299.768us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 868.060s 299.768us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 19.990s 4151.350us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 19.990s 4151.350us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 19.990s 4151.350us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 194.580s 268.354us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 390.490s 13951.156us 1 1 100.00
rom_ctrl_kmac_err_chk 22.660s 59.814us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 390.490s 13951.156us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 390.490s 13951.156us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 390.490s 13951.156us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 38.820s 172.879us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 868.060s 299.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 59.520s 18084.076us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 77760234775535418834520003821703409393088616584379964280635211065888174625031 85
UVM_INFO @ 1006678515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---