Simulation Results: rstmgr

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 97.63 %
  • code
  • 99.08 %
  • assert
  • 98.53 %
  • func
  • 95.27 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.06 %
  • toggle
  • 98.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.480s 249.025us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.010s 118.115us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.830s 82.956us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 5.470s 1448.001us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.030s 85.783us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.100s 104.772us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.830s 82.956us 1 1 100.00
rstmgr_csr_aliasing 1.030s 85.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.910s 106.119us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.560s 164.079us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.480s 185.866us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.540s 1881.915us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.540s 1881.915us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.540s 1881.915us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.540s 1881.915us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 8.970s 2510.674us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.070s 85.948us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.320s 100.747us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.320s 100.747us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.010s 118.115us 1 1 100.00
rstmgr_csr_rw 0.830s 82.956us 1 1 100.00
rstmgr_csr_aliasing 1.030s 85.783us 1 1 100.00
rstmgr_same_csr_outstanding 1.080s 80.196us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.010s 118.115us 1 1 100.00
rstmgr_csr_rw 0.830s 82.956us 1 1 100.00
rstmgr_csr_aliasing 1.030s 85.783us 1 1 100.00
rstmgr_same_csr_outstanding 1.080s 80.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 22.760s 16867.502us 1 1 100.00
rstmgr_tl_intg_err 3.030s 953.037us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 22.760s 16867.502us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 22.760s 16867.502us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.030s 953.037us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.120s 119.864us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.440s 1406.798us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.360s 301.485us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 22.760s 16867.502us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.830s 82.956us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.830s 82.956us 1 1 100.00