Simulation Results: rv_timer

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 93.73 %
  • code
  • 94.66 %
  • assert
  • 96.82 %
  • func
  • 89.71 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.760s 259.105us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.560s 69.501us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.530s 23.477us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.220s 644.231us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.580s 13.398us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.250s 58.490us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.530s 23.477us 1 1 100.00
rv_timer_csr_aliasing 0.580s 13.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 0.860s 140.282us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.330s 1684.172us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.960s 406.753us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.960s 406.753us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.830s 1940.696us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.650s 41.189us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.630s 14.409us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.290s 185.641us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.290s 185.641us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 69.501us 1 1 100.00
rv_timer_csr_rw 0.530s 23.477us 1 1 100.00
rv_timer_csr_aliasing 0.580s 13.398us 1 1 100.00
rv_timer_same_csr_outstanding 0.590s 33.563us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 69.501us 1 1 100.00
rv_timer_csr_rw 0.530s 23.477us 1 1 100.00
rv_timer_csr_aliasing 0.580s 13.398us 1 1 100.00
rv_timer_same_csr_outstanding 0.590s 33.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.720s 39.995us 1 1 100.00
rv_timer_tl_intg_err 1.010s 94.819us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.010s 94.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.770s 225.318us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.670s 178.589us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 35.090s 18086.301us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 59079680535954291294045011305552847994075334385843099143795745980430858864022 82
UVM_INFO @ 225317982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 85584880421857507333054356595729128302328196268670365455916633063428570302715 81
UVM_INFO @ 178589304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---