Simulation Results: spi_device/1r1w

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 85.20 %
  • code
  • 91.33 %
  • assert
  • 95.27 %
  • func
  • 69.00 %
  • line
  • 98.89 %
  • branch
  • 98.22 %
  • cond
  • 95.88 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 68.770s 20631.257us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.850s 69.180us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.880s 292.278us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 22.350s 4572.888us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 1.440s 47.049us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.430s 60.027us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.880s 292.278us 1 1 100.00
spi_device_csr_aliasing 1.440s 47.049us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.730s 65.192us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.400s 50.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.740s 39.399us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.830s 2.802us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.860s 3.044us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.700s 11.354us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.700s 11.354us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 4.140s 8648.375us 1 1 100.00
spi_device_tpm_sts_read 0.770s 416.755us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 13.610s 12251.239us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 20.030s 7998.558us 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.810s 957.465us 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.810s 957.465us 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 7.040s 1139.151us 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 7.040s 1139.151us 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 7.040s 1139.151us 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 7.040s 1139.151us 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 7.040s 1139.151us 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 1.950s 79.664us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.870s 72.689us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.870s 72.689us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.870s 72.689us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 11.030s 11509.406us 1 1 100.00
spi_device_read_buffer_direct 9.530s 5356.230us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.870s 72.689us 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 56.410s 54459.928us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.010s 75.854us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.010s 75.854us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 187.950s 46619.639us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 68.770s 20631.257us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 158.800s 38534.615us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 321.440s 186609.604us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.670s 13.834us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.740s 24.214us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.100s 89.343us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.100s 89.343us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.850s 69.180us 1 1 100.00
spi_device_csr_rw 1.880s 292.278us 1 1 100.00
spi_device_csr_aliasing 1.440s 47.049us 1 1 100.00
spi_device_same_csr_outstanding 2.120s 78.600us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.850s 69.180us 1 1 100.00
spi_device_csr_rw 1.880s 292.278us 1 1 100.00
spi_device_csr_aliasing 1.440s 47.049us 1 1 100.00
spi_device_same_csr_outstanding 2.120s 78.600us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.910s 1073.469us 1 1 100.00
spi_device_tl_intg_err 7.450s 398.725us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 7.450s 398.725us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1661) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 91645237766012240103457957799463842213101961386435839028286100386319260883037 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2262454 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2262454 ps: (uvm_hdl_vcs.c:2025) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[971])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 55725366051417462601635385985178843892186401399833054272942677148492375838255 76
UVM_ERROR @ 891007 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x317 [1100010111] vs 0x0 [0])
UVM_ERROR @ 949007 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1a [11010] vs 0x0 [0])
UVM_ERROR @ 1006007 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb5 [10110101] vs 0x0 [0])
UVM_ERROR @ 1060007 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1a2 [110100010] vs 0x0 [0])