Simulation Results: spi_host

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 92.05 %
  • code
  • 91.30 %
  • assert
  • 96.60 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 27.000s 5901.669us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 17.263us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 45.213us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 1.000s 156.099us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 7.000s 19.766us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 48.432us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 45.213us 1 1 100.00
spi_host_csr_aliasing 7.000s 19.766us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 39.862us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 24.838us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 8.000s 23.562us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 9.000s 297.337us 1 1 100.00
spi_host_error_cmd 8.000s 25.394us 1 1 100.00
spi_host_event 10.000s 277.091us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 8.000s 51.688us 1 1 100.00
speed 1 1 100.00
spi_host_speed 8.000s 51.688us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 8.000s 51.688us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 236.000s 27995.640us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 18.000s 888.494us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 7.000s 25.049us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 8.000s 51.688us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 8.000s 51.688us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 27.000s 5901.669us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 27.000s 5901.669us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 10.000s 578.988us 1 1 100.00
spien 1 1 100.00
spi_host_spien 9.000s 1428.020us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 14.000s 1464.772us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 9.000s 96.410us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 9.000s 297.337us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 8.000s 53.802us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 39.425us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 40.014us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 40.014us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 17.263us 1 1 100.00
spi_host_csr_rw 1.000s 45.213us 1 1 100.00
spi_host_csr_aliasing 7.000s 19.766us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 46.100us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 17.263us 1 1 100.00
spi_host_csr_rw 1.000s 45.213us 1 1 100.00
spi_host_csr_aliasing 7.000s 19.766us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 46.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 159.134us 1 1 100.00
spi_host_sec_cm 8.000s 154.640us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 159.134us 1 1 100.00