Simulation Results: sram_ctrl/main

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.45 %
  • code
  • 93.73 %
  • assert
  • 97.42 %
  • func
  • 95.20 %
  • block
  • 92.73 %
  • line
  • 93.64 %
  • branch
  • 89.45 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 6.000s 683.077us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 25.266us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.755us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 230.349us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.241us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 362.147us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 12.755us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.241us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 137.000s 3085.184us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 100.000s 1647.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 43.000s 6281.538us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 181.000s 7268.627us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 217.000s 18241.715us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 98.000s 151402.352us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 16.000s 5220.505us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 35.000s 20379.688us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 5.000s 1441.690us 1 1 100.00
sram_ctrl_partial_access_b2b 277.000s 117600.634us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 695.628us 1 1 100.00
sram_ctrl_throughput_w_partial_write 7.000s 2859.116us 1 1 100.00
sram_ctrl_throughput_w_readback 6.000s 4450.658us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1029.374us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 392.037us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 6.000s 683.077us 1 1 100.00
sram_ctrl_partial_access 5.000s 1441.690us 1 1 100.00
sram_ctrl_access_during_key_req 98.000s 151402.352us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 116.000s 27083.139us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 34.754us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 475.410us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 475.410us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 25.266us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.755us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.241us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 12.884us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 25.266us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.755us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 42.241us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 12.884us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 3838.588us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 622.173us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 219.096us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 622.173us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 219.096us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1029.374us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1029.374us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.755us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 35.000s 20379.688us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 35.000s 20379.688us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 35.000s 20379.688us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 16.000s 5220.505us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 14.000s 3838.588us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 683.077us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 6.000s 683.077us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 35.000s 20379.688us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 622.173us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 16.000s 5220.505us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 622.173us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 622.173us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 6.000s 683.077us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 622.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.000s 231.999us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 65316375497076116502354699975814797049534102714893136087488379965421051130611 None
sram_ctrl_mubi_enc_err 16181873387605125100546996878451093170024577280167599507126328155515896329489 None