Simulation Results: sram_ctrl/ret

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.60 %
  • code
  • 81.71 %
  • assert
  • 97.12 %
  • func
  • 92.96 %
  • block
  • 92.12 %
  • line
  • 93.78 %
  • branch
  • 88.07 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 63.811us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 17.438us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 19.553us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 57.374us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.954us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 45.267us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 19.553us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.954us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.000s 1649.817us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 421.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 5.000s 500.660us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 234.000s 4514.089us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 8.000s 503.414us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 20.000s 2140.318us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 11.000s 1089.118us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 13.000s 10628.046us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 77.878us 1 1 100.00
sram_ctrl_partial_access_b2b 113.000s 2218.078us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 36.442us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 358.884us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 41.650us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 406.591us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 40.756us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 2.000s 63.811us 1 1 100.00
sram_ctrl_partial_access 3.000s 77.878us 1 1 100.00
sram_ctrl_access_during_key_req 20.000s 2140.318us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 44.000s 8201.977us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 15.651us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 46.872us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 46.872us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.438us 1 1 100.00
sram_ctrl_csr_rw 2.000s 19.553us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.954us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 97.347us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 17.438us 1 1 100.00
sram_ctrl_csr_rw 2.000s 19.553us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.954us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 97.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 210.416us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 396.853us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 215.396us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 396.853us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 215.396us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 406.591us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 406.591us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 19.553us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 13.000s 10628.046us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 10628.046us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 13.000s 10628.046us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 11.000s 1089.118us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3602.182s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 210.416us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3602.169s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 63.811us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 63.811us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 13.000s 10628.046us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 396.853us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 11.000s 1089.118us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 396.853us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 396.853us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 63.811us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 396.853us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 54.000s 2096.431us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 29038464950617469931327910528892232780083007549612957414450147430131863465928 None
sram_ctrl_mubi_enc_err 82853048432584752846943878810955928331498616478184210916196261643333152451334 None