Simulation Results: sysrst_ctrl

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.81 %
  • code
  • 81.44 %
  • assert
  • 82.39 %
  • func
  • 63.60 %
  • line
  • 91.83 %
  • branch
  • 92.32 %
  • cond
  • 90.87 %
  • toggle
  • 98.86 %
  • FSM
  • 33.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
50.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.590s 2130.232us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.120s 2464.541us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.710s 2217.933us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.800s 2544.020us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 4.280s 4018.218us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.590s 2082.646us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 126.180s 74579.270us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.800s 2172.937us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.120s 2048.444us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.590s 2082.646us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.800s 2172.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 16.100s 39111.634us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 14.780s 30207.853us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.780s 3407.476us 1 1 100.00
keyboard_input_triggered_interrupt 0 1 0.00
sysrst_ctrl_edge_detect 4.780s 3334.504us 0 1 0.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 1.860s 2535.044us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 5.530s 2187.716us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 7.470s 3795.177us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 6.040s 2611.934us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.360s 3508.447us 1 1 100.00
sysrst_ctrl_feature_disable 0 1 0.00
sysrst_ctrl_feature_disable 78.330s 36579.157us 0 1 0.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 197.790s 284011.573us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.620s 2046.018us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.130s 2023.178us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.900s 2479.072us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.900s 2479.072us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.280s 4018.218us 1 1 100.00
sysrst_ctrl_csr_rw 2.590s 2082.646us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.800s 2172.937us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.800s 5380.883us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 4.280s 4018.218us 1 1 100.00
sysrst_ctrl_csr_rw 2.590s 2082.646us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.800s 2172.937us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 3.800s 5380.883us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
sysrst_ctrl_sec_cm 6.040s 22194.162us 0 1 0.00
sysrst_ctrl_tl_intg_err 40.310s 22254.442us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 40.310s 22254.442us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.370s 4769.724us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 2 test runs
sysrst_ctrl_edge_detect 419682675926923940838070372922510725339105816241280244374490169046901160712 665
UVM_ERROR @ 3334504383 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3334504383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_feature_disable 3004027911714921516108349173143739363318061006916588132798594841638155275149 691
UVM_ERROR @ 36579157087 ps: (cip_base_scoreboard.sv:268) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 36579157087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [sysrst_ctrl_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
sysrst_ctrl_sec_cm 83895501268186287090957139099781919061283150874411582279214628021562324374708 668
UVM_INFO @ 6035905215 ps: (cip_base_vseq__sec_cm_fi.svh:8) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running run_sec_cm_fi_vseq 3/10
UVM_INFO @ 6035950669 ps: (prim_onehot_check_if.sv:103) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\prim_onehot_check_if_proxy::inject_fault ] onehot_fault_type: OnehotFault
UVM_INFO @ 6035950669 ps: (prim_onehot_check_if.sv:107) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\prim_onehot_check_if_proxy::inject_fault ] Forcing tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.en_i from 0 to 1, tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.oh_i from 0 to 4759021106087 and tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.addr_i from 0 to 52
UVM_INFO @ 6036041578 ps: (prim_onehot_check_if.sv:124) [tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if.\prim_onehot_check_if_proxy::restore_fault ] Restoring original value of tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.en_i (0), tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.oh_i (0) and tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.addr_i (0)