Simulation Results: uart

 
03/09/2026 19:45:14 DVSim: v1.52.1 sha: 119f86a json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.54 %
  • code
  • 91.62 %
  • assert
  • 97.98 %
  • func
  • 64.00 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.22 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.050s 439.120us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.550s 12.849us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.620s 34.991us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.390s 563.937us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.610s 41.402us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.670s 114.477us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.620s 34.991us 1 1 100.00
uart_csr_aliasing 0.610s 41.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 59.470s 49929.266us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.050s 439.120us 1 1 100.00
uart_tx_rx 59.470s 49929.266us 1 1 100.00
parity_error 2 2 100.00
uart_intr 42.800s 35391.257us 1 1 100.00
uart_rx_parity_err 8.380s 42676.171us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 59.470s 49929.266us 1 1 100.00
uart_intr 42.800s 35391.257us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 60.600s 47014.109us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 51.290s 88566.978us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 35.000s 36380.880us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 42.800s 35391.257us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 42.800s 35391.257us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 42.800s 35391.257us 1 1 100.00
perf 1 1 100.00
uart_perf 81.440s 19547.094us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 13.110s 6744.758us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 13.110s 6744.758us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 41.020s 58845.115us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.100s 2750.287us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.480s 1147.366us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 16.360s 3471.349us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 534.250s 116934.237us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 238.510s 1613473.251us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.650s 42.213us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.590s 50.156us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.800s 82.595us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.800s 82.595us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.550s 12.849us 1 1 100.00
uart_csr_rw 0.620s 34.991us 1 1 100.00
uart_csr_aliasing 0.610s 41.402us 1 1 100.00
uart_same_csr_outstanding 0.730s 96.859us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.550s 12.849us 1 1 100.00
uart_csr_rw 0.620s 34.991us 1 1 100.00
uart_csr_aliasing 0.610s 41.402us 1 1 100.00
uart_same_csr_outstanding 0.730s 96.859us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.780s 88.882us 1 1 100.00
uart_tl_intg_err 1.300s 97.497us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.300s 97.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 20.950s 5019.564us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 101956635743514342273764413660935811933976673001336908289089366985221730070585 93
UVM_ERROR @ 54340791264 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 54340812097 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (104 [0x68] vs 252 [0xfc]) reg name: uart_reg_block.rdata
UVM_ERROR @ 54342166242 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 54342207908 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty