Simulation Results: aes/masked

 
07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.71 %
  • code
  • 93.32 %
  • assert
  • 98.23 %
  • func
  • 74.57 %
  • block
  • 93.73 %
  • line
  • 95.43 %
  • branch
  • 86.52 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
85.71%
V2
88.24%
V2S
62.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 60.752us 1 1 100.00
smoke 0 1 0.00
aes_smoke 106.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 6.000s 194.575us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 57.026us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 724.645us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 1.000s 59.548us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 143.835us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 57.026us 1 1 100.00
aes_csr_aliasing 1.000s 59.548us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 2 3 66.67
aes_smoke 106.000s 0.000us 0 1 0.00
aes_config_error 2.000s 104.619us 1 1 100.00
aes_stress 6.000s 70.448us 1 1 100.00
key_length 2 3 66.67
aes_smoke 106.000s 0.000us 0 1 0.00
aes_config_error 2.000s 104.619us 1 1 100.00
aes_stress 6.000s 70.448us 1 1 100.00
back2back 2 2 100.00
aes_stress 6.000s 70.448us 1 1 100.00
aes_b2b 3.000s 130.965us 1 1 100.00
backpressure 1 1 100.00
aes_stress 6.000s 70.448us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 106.000s 0.000us 0 1 0.00
aes_config_error 2.000s 104.619us 1 1 100.00
aes_stress 6.000s 70.448us 1 1 100.00
aes_alert_reset 3.000s 692.113us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 59.320us 1 1 100.00
aes_config_error 2.000s 104.619us 1 1 100.00
aes_alert_reset 3.000s 692.113us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 190.422us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 2556.342us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 692.113us 1 1 100.00
stress 1 1 100.00
aes_stress 6.000s 70.448us 1 1 100.00
sideload 2 2 100.00
aes_stress 6.000s 70.448us 1 1 100.00
aes_sideload 3.000s 115.827us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 1.000s 102.240us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 21.000s 446.760us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 87.580us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 143.127us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 143.127us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 6.000s 194.575us 1 1 100.00
aes_csr_rw 1.000s 57.026us 1 1 100.00
aes_csr_aliasing 1.000s 59.548us 1 1 100.00
aes_same_csr_outstanding 1.000s 104.776us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 6.000s 194.575us 1 1 100.00
aes_csr_rw 1.000s 57.026us 1 1 100.00
aes_csr_aliasing 1.000s 59.548us 1 1 100.00
aes_same_csr_outstanding 1.000s 104.776us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 1.000s 75.880us 0 1 0.00
fault_inject 0 3 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 175.623us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 175.623us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 175.623us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 175.623us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 7.000s 117.878us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 470.156us 1 1 100.00
aes_tl_intg_err 7.000s 390.165us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 7.000s 390.165us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 692.113us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 175.623us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 175.623us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 106.000s 0.000us 0 1 0.00
aes_stress 6.000s 70.448us 1 1 100.00
aes_alert_reset 3.000s 692.113us 1 1 100.00
aes_core_fi 1.000s 125.603us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 104.619us 1 1 100.00
aes_stress 6.000s 70.448us 1 1 100.00
aes_core_fi 1.000s 125.603us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 175.623us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 190.559us 1 1 100.00
aes_stress 6.000s 70.448us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 6.000s 70.448us 1 1 100.00
aes_sideload 3.000s 115.827us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 190.559us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 190.559us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 190.559us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 190.559us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 190.559us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 6.000s 70.448us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 6.000s 70.448us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
sec_cm_main_fsm_redun 0 4 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 59.000s 0.000us 0 1 0.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
sec_cm_cipher_fsm_redun 0 3 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
sec_cm_ctr_fsm_redun 0 3 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 59.000s 0.000us 0 1 0.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
sec_cm_ctrl_sparse 0 4 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 59.000s 0.000us 0 1 0.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 692.113us 1 1 100.00
sec_cm_main_fsm_local_esc 0 4 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 59.000s 0.000us 0 1 0.00
sec_cm_cipher_fsm_local_esc 0 4 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 59.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_local_esc 0 3 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 59.000s 0.000us 0 1 0.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
sec_cm_data_reg_local_esc 0 3 0.00
aes_fi 3.000s 1233.176us 0 1 0.00
aes_control_fi 60.000s 0.000us 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 20.000s 2050.304us 0 1 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
aes_smoke 113312616737928177121448523892263204871787926139195216007422818792510489333290 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:17:01 UTC (total: 00:01:46)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
aes_ctr_fi 47755647677126063009476962128718307074125777783031328275198354382337919256178 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:16:32 UTC (total: 00:00:59)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 78697111634574096242733679810449057754890259954657287491858917207219816269169 1177
UVM_INFO @ 75880286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 57306899859293617500004979443150467105071960761091315710646637471874558475307 46882
UVM_INFO @ 446759568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 2 test runs
aes_control_fi 19994016532854763720522384948755651715066456068648221829736197811309129810694 None
aes_cipher_fi 28963633919681559391196160971289842891036120995641329290043833324417866150353 None
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 93158896384930019913066196754735370801609371670318501577931012018440132109050 14269
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 5
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 34448174845832525919163414556908960038406772078219303359691729934525634438672 573
UVM_INFO @ 2050303827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---