| V1 |
|
100.00% |
| V2 |
|
88.24% |
| V2S |
|
62.50% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 1.000s | 283.025us | 1 | 1 | 100.00 | |
| smoke | 1 | 1 | 100.00 | |||
| aes_smoke | 3.000s | 193.317us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aes_csr_hw_reset | 1.000s | 108.342us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| aes_csr_rw | 1.000s | 158.423us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aes_csr_bit_bash | 3.000s | 890.481us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aes_csr_aliasing | 1.000s | 100.641us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 1.000s | 89.363us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| aes_csr_rw | 1.000s | 158.423us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 1.000s | 100.641us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 2 | 3 | 66.67 | |||
| aes_smoke | 3.000s | 193.317us | 1 | 1 | 100.00 | |
| aes_config_error | 1.000s | 173.093us | 1 | 1 | 100.00 | |
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| key_length | 2 | 3 | 66.67 | |||
| aes_smoke | 3.000s | 193.317us | 1 | 1 | 100.00 | |
| aes_config_error | 1.000s | 173.093us | 1 | 1 | 100.00 | |
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| back2back | 1 | 2 | 50.00 | |||
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_b2b | 3.000s | 123.168us | 1 | 1 | 100.00 | |
| backpressure | 0 | 1 | 0.00 | |||
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| multi_message | 3 | 4 | 75.00 | |||
| aes_smoke | 3.000s | 193.317us | 1 | 1 | 100.00 | |
| aes_config_error | 1.000s | 173.093us | 1 | 1 | 100.00 | |
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_alert_reset | 2.000s | 99.084us | 1 | 1 | 100.00 | |
| failure_test | 3 | 3 | 100.00 | |||
| aes_man_cfg_err | 2.000s | 71.662us | 1 | 1 | 100.00 | |
| aes_config_error | 1.000s | 173.093us | 1 | 1 | 100.00 | |
| aes_alert_reset | 2.000s | 99.084us | 1 | 1 | 100.00 | |
| trigger_clear_test | 1 | 1 | 100.00 | |||
| aes_clear | 2.000s | 113.452us | 1 | 1 | 100.00 | |
| nist_test_vectors | 0 | 1 | 0.00 | |||
| aes_nist_vectors | 73.000s | 0.000us | 0 | 1 | 0.00 | |
| reset_recovery | 1 | 1 | 100.00 | |||
| aes_alert_reset | 2.000s | 99.084us | 1 | 1 | 100.00 | |
| stress | 0 | 1 | 0.00 | |||
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| sideload | 1 | 2 | 50.00 | |||
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_sideload | 2.000s | 67.529us | 1 | 1 | 100.00 | |
| deinitialization | 1 | 1 | 100.00 | |||
| aes_deinit | 1.000s | 84.910us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| aes_stress_all | 5.000s | 1584.438us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| aes_alert_test | 1.000s | 142.783us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 1.000s | 140.348us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| aes_tl_errors | 1.000s | 140.348us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 1.000s | 108.342us | 1 | 1 | 100.00 | |
| aes_csr_rw | 1.000s | 158.423us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 1.000s | 100.641us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 81.505us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| aes_csr_hw_reset | 1.000s | 108.342us | 1 | 1 | 100.00 | |
| aes_csr_rw | 1.000s | 158.423us | 1 | 1 | 100.00 | |
| aes_csr_aliasing | 1.000s | 100.641us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 2.000s | 81.505us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 0 | 1 | 0.00 | |||
| aes_reseed | 103.000s | 0.000us | 0 | 1 | 0.00 | |
| fault_inject | 0 | 3 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| aes_control_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 67.552us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 67.552us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 67.552us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 67.552us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 2.000s | 182.582us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| aes_sec_cm | 1.000s | 290.500us | 1 | 1 | 100.00 | |
| aes_tl_intg_err | 1.000s | 162.597us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| aes_tl_intg_err | 1.000s | 162.597us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| aes_alert_reset | 2.000s | 99.084us | 1 | 1 | 100.00 | |
| sec_cm_main_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 67.552us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 67.552us | 1 | 1 | 100.00 | |
| sec_cm_main_config_sparse | 3 | 4 | 75.00 | |||
| aes_smoke | 3.000s | 193.317us | 1 | 1 | 100.00 | |
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_alert_reset | 2.000s | 99.084us | 1 | 1 | 100.00 | |
| aes_core_fi | 1.000s | 176.784us | 1 | 1 | 100.00 | |
| sec_cm_gcm_config_sparse | 2 | 3 | 66.67 | |||
| aes_config_error | 1.000s | 173.093us | 1 | 1 | 100.00 | |
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_core_fi | 1.000s | 176.784us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_shadow | 1 | 1 | 100.00 | |||
| aes_shadow_reg_errors | 1.000s | 67.552us | 1 | 1 | 100.00 | |
| sec_cm_aux_config_regwen | 1 | 2 | 50.00 | |||
| aes_readability | 1.000s | 68.917us | 1 | 1 | 100.00 | |
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_key_sideload | 1 | 2 | 50.00 | |||
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_sideload | 2.000s | 67.529us | 1 | 1 | 100.00 | |
| sec_cm_key_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 1.000s | 68.917us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 1 | 1 | 100.00 | |||
| aes_readability | 1.000s | 68.917us | 1 | 1 | 100.00 | |
| sec_cm_key_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 1.000s | 68.917us | 1 | 1 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 1.000s | 68.917us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 1 | 1 | 100.00 | |||
| aes_readability | 1.000s | 68.917us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_key_sca | 0 | 1 | 0.00 | |||
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_key_masking | 0 | 1 | 0.00 | |||
| aes_stress | 101.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_redun | 0 | 4 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| aes_control_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cipher_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| sec_cm_cipher_fsm_redun | 0 | 3 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| aes_control_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cipher_ctr_redun | 0 | 1 | 0.00 | |||
| aes_cipher_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| sec_cm_ctr_fsm_redun | 0 | 3 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| aes_control_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ghash_fsm_sparse | 0 | 1 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_sparse | 0 | 4 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| aes_control_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_global_esc | 1 | 1 | 100.00 | |||
| aes_alert_reset | 2.000s | 99.084us | 1 | 1 | 100.00 | |
| sec_cm_main_fsm_local_esc | 0 | 4 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| aes_control_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cipher_fsm_local_esc | 0 | 4 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| aes_control_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_fsm_local_esc | 0 | 3 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| aes_control_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_ctr_fi | 16.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ghash_fsm_local_esc | 0 | 1 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_local_esc | 0 | 3 | 0.00 | |||
| aes_fi | 1.000s | 15.563us | 0 | 1 | 0.00 | |
| aes_control_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| aes_cipher_fi | 60.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| aes_stress_all_with_rand_reset | 100.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 5 test runs | |||
| aes_nist_vectors | 37265094475998605184723026083730220774816176914935887310784393019068419061049 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:16:32 UTC (total: 00:01:13)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| aes_stress | 80984136465254352314103075715480715172896837614165591475807390299870743215623 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:17:01 UTC (total: 00:01:41)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| aes_reseed | 77785953653629791300132645926677644033704519853359976292230774623907900821828 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:17:02 UTC (total: 00:01:43)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| aes_ctr_fi | 81366225964116807706267937107749894600002865511726510315629740351476804610631 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:18:14 UTC (total: 00:00:16)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| aes_stress_all_with_rand_reset | 50661331419591527821044948549332517118742918263900278233913954955437617081404 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:17:01 UTC (total: 00:01:40)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| Job timed out after * minutes | 2 test runs | |||
| aes_control_fi | 26129809522379857913817241596926417936081927390960789672619993658474127117038 | None | ||
| aes_cipher_fi | 92979659089669720387144176883389355873103452753834785038716826585003761156744 | None | ||
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1143): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) | 1 test run | |||
| aes_fi | 106625675899305834539553668439102475787285139606876969561341219524809783500157 | 1686 |
UVM_ERROR @ 15563300 ps: (aes_core.sv:1143) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 15563300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|