Simulation Results: alert_handler

 
07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 81.74 %
  • code
  • 90.41 %
  • assert
  • 90.66 %
  • func
  • 64.16 %
  • line
  • 99.68 %
  • branch
  • 96.70 %
  • cond
  • 87.64 %
  • toggle
  • 89.01 %
  • FSM
  • 79.03 %
Validation stages
V1
16.67%
V2
57.89%
V2S
62.50%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 22.660s 2033.473us 1 1 100.00
csr_hw_reset 0 1 0.00
alert_handler_csr_hw_reset 0.000s 0.000us 0 1 0.00
csr_rw 0 1 0.00
alert_handler_csr_rw 0.000s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
alert_handler_csr_bit_bash 0.000s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
alert_handler_csr_aliasing 0.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
alert_handler_csr_mem_rw_with_rand_reset 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
alert_handler_csr_rw 0.000s 0.000us 0 1 0.00
alert_handler_csr_aliasing 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 26.050s 2991.512us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 23.850s 1094.524us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 941.080s 49146.043us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 9.170s 317.099us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 22.660s 2033.473us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 3.800s 359.662us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 37.080s 1536.904us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 66.560s 27363.219us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 910.160s 96027.726us 1 1 100.00
alert_handler_lpg_stub_clk 555.170s 98854.204us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 24.660s 6579.769us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 4.110s 317.917us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.750s 226.056us 1 1 100.00
intr_test 0 1 0.00
alert_handler_intr_test 0.000s 0.000us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
alert_handler_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
alert_handler_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_outstanding_access 0 4 0.00
alert_handler_csr_hw_reset 0.000s 0.000us 0 1 0.00
alert_handler_csr_rw 0.000s 0.000us 0 1 0.00
alert_handler_csr_aliasing 0.000s 0.000us 0 1 0.00
alert_handler_same_csr_outstanding 0.000s 0.000us 0 1 0.00
tl_d_partial_access 0 4 0.00
alert_handler_csr_hw_reset 0.000s 0.000us 0 1 0.00
alert_handler_csr_rw 0.000s 0.000us 0 1 0.00
alert_handler_csr_aliasing 0.000s 0.000us 0 1 0.00
alert_handler_same_csr_outstanding 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 0 1 0.00
alert_handler_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
alert_handler_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
alert_handler_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
alert_handler_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
alert_handler_shadow_reg_errors_with_csr_rw 0.000s 0.000us 0 1 0.00
tl_intg_err 1 2 50.00
alert_handler_sec_cm 10.550s 1908.927us 1 1 100.00
alert_handler_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
alert_handler_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_config_shadow 0 1 0.00
alert_handler_shadow_reg_errors 0.000s 0.000us 0 1 0.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 22.660s 2033.473us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 22.660s 2033.473us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 22.660s 2033.473us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 22.660s 2033.473us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 9.170s 317.099us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 910.160s 96027.726us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 9.170s 317.099us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 941.080s 49146.043us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 941.080s 49146.043us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.550s 1908.927us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 10.550s 1908.927us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.550s 1908.927us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 10.550s 1908.927us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 10.550s 1908.927us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.550s 1908.927us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.550s 1908.927us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 10.550s 1908.927us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 10.550s 1908.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 153.890s 18772.963us 1 1 100.00

Error Messages

   Test seed line log context
Job cancelled because one of its dependencies failed or was killed. 11 test runs
alert_handler_shadow_reg_errors_with_csr_rw 113988110741646162460327325580774605792060862923015212404787280697468961199775 None
alert_handler_shadow_reg_errors 75029576442133984402107288904716966544187979523295999604042238390455704933273 None
alert_handler_tl_errors 7538006295276216981945512840391183777733404102403882324879807975661496458495 None
alert_handler_tl_intg_err 98806239382088813035955066964834216811570779223295999881413844266965482781366 None
alert_handler_intr_test 85794967997360486141003428018878477149340145683679870049181745600442357500888 None
alert_handler_csr_hw_reset 84499863778170632007721638042209494180958230285525596163561783191568424178830 None
alert_handler_csr_rw 88864088647022608070933888605083944212332515261180655101503011816736561459797 None
alert_handler_csr_bit_bash 112520519149810875136387002401833428459445342963916992489260388267023285479762 None
alert_handler_csr_aliasing 40571704787369237559596103151307377552307985747863168944015611523078177111288 None
alert_handler_same_csr_outstanding 49163391890210567287585123096578890131620325079352887209431574508053125252300 None
alert_handler_csr_mem_rw_with_rand_reset 61644718199862157348107966664422329357688139375015636888011200777902435981691 None
Job returned a non-zero exit code: * 1 test run
cover_reg_top None None
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.148 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 49043774195252893417585208453495123431869212196373771919332857239353475920366 108
UVM_INFO @ 27363219147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 14767542829816815644481783090304405696622698433067526481249856445803406753986 214
UVM_INFO @ 317916842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---