| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| clkmgr_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 0 | 1 | 0.00 | |||
| clkmgr_peri | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| trans_enables | 0 | 1 | 0.00 | |||
| clkmgr_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| extclk | 0 | 1 | 0.00 | |||
| clkmgr_extclk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clk_status | 0 | 1 | 0.00 | |||
| clkmgr_clk_status | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jitter | 0 | 1 | 0.00 | |||
| clkmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_timeout | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| frequency_overflow | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| clkmgr_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| clkmgr_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| clkmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| clkmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_storage_error | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadowed_reset_glitch | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| clkmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timeout_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| clkmgr_frequency_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_shadow | 0 | 1 | 0.00 | |||
| clkmgr_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_idle_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_lc_ctrl_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_ctrl_clk_handshake_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_lc_clk_byp_req_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_clk_handshake_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_clk_handshake_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_div_intersig_mubi | 0 | 1 | 0.00 | |||
| clkmgr_div_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_jitter_config_mubi | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_idle_ctr_redun | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_meas_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_clk_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| clkmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| clkmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 0 | 1 | 0.00 | |||
| clkmgr_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| clkmgr_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 28 test runs | |||
| clkmgr_smoke | 67615105356285084101953344467337435415460276946205888859757368649219319350291 | None | ||
| clkmgr_extclk | 97012788486602370770932090909270188630898878746490452294117536833294589891501 | None | ||
| clkmgr_frequency | 45065462915656398149268817074576605771893483609874783434864973558110427810918 | None | ||
| clkmgr_frequency_timeout | 6193938674863347659319732463118001135299698294970338486300541747927714186222 | None | ||
| clkmgr_peri | 102449210165226154714702186871531090562216383466659185179863609244591859927618 | None | ||
| clkmgr_trans | 32607265279861958045531231850052554573231969141399800423491972820705569465445 | None | ||
| clkmgr_clk_status | 74716061366006001697968197101973537145283115759216479020512829950285162242094 | None | ||
| clkmgr_idle_intersig_mubi | 8758818610252463949132280364064307757164717844285632737380061103082254088832 | None | ||
| clkmgr_lc_ctrl_intersig_mubi | 5780114723617605249631661946398179393069636408449701809428638884139620184474 | None | ||
| clkmgr_lc_clk_byp_req_intersig_mubi | 115562600297431872939812700089819256459557459429341414693136788734158272408897 | None | ||
| clkmgr_clk_handshake_intersig_mubi | 370040733979325575568765441648395599015771016306288487104565152400125562667 | None | ||
| clkmgr_div_intersig_mubi | 82437000621886426867080795472122121421025094051636309585635906261462256882740 | None | ||
| clkmgr_regwen | 3753990780301744739341865002614196411905568887009543084124217111742337184136 | None | ||
| clkmgr_shadow_reg_errors | 51330382524374355084822108716963684754863014772961350677342838457311697588737 | None | ||
| clkmgr_shadow_reg_errors_with_csr_rw | 43917652381605661262607490414982183648741677618993526180839139058320109060466 | None | ||
| clkmgr_sec_cm | 5624492876192475500753567824773243794898811906378046411489270374591876239210 | None | ||
| clkmgr_stress_all_with_rand_reset | 48716114644960054541935154167353398752595245056699892205384964177963905120508 | None | ||
| clkmgr_stress_all | 61522006433338084065418920860364945427065442698633245462835489199428907508013 | None | ||
| clkmgr_tl_errors | 85257329944061338340571466969871623602075282770434347034331382156330918170484 | None | ||
| clkmgr_tl_intg_err | 6088572176939717566906894612878306568574872047989149062697115504751220745711 | None | ||
| clkmgr_alert_test | 54501169006469445386155392959944334476731779618870534114037580720250588894779 | None | ||
| clkmgr_csr_hw_reset | 114908410132731103338908542272551088889743163031525422192450386792617702965634 | None | ||
| clkmgr_csr_rw | 32273095750382107839963105364214634223128034844680631039120971028817538020821 | None | ||
| clkmgr_csr_bit_bash | 11043707449972972511626146030523507606869776629630616613163423602600951410271 | None | ||
| clkmgr_csr_aliasing | 36540947020671054097585743143286933126502586620117186627048164804660665364730 | None | ||
| clkmgr_same_csr_outstanding | 76814312287328296137529035995532471949658756544835290863218851976594039194088 | None | ||
| clkmgr_csr_mem_rw_with_rand_reset | 72180676883911873700151370180430221693614860261063725615481941412315311636985 | None | ||
| clkmgr | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.158 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.146 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| clkmgr | None | None | ||