| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
87.50% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| csrng_smoke | 11.000s | 30.526us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| csrng_csr_hw_reset | 1.000s | 25.381us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| csrng_csr_rw | 1.000s | 14.056us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| csrng_csr_bit_bash | 31.000s | 4061.992us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| csrng_csr_aliasing | 1.000s | 31.575us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| csrng_csr_mem_rw_with_rand_reset | 1.000s | 19.361us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| csrng_csr_rw | 1.000s | 14.056us | 1 | 1 | 100.00 | |
| csrng_csr_aliasing | 1.000s | 31.575us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| interrupts | 1 | 1 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| alerts | 1 | 1 | 100.00 | |||
| csrng_alert | 16.000s | 737.421us | 1 | 1 | 100.00 | |
| err | 1 | 1 | 100.00 | |||
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| cmds | 1 | 1 | 100.00 | |||
| csrng_cmds | 27.000s | 1907.784us | 1 | 1 | 100.00 | |
| life cycle | 1 | 1 | 100.00 | |||
| csrng_cmds | 27.000s | 1907.784us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| csrng_stress_all | 133.000s | 13329.624us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| csrng_intr_test | 1.000s | 25.947us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| csrng_alert_test | 1.000s | 19.301us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| csrng_tl_errors | 7.000s | 123.863us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| csrng_tl_errors | 7.000s | 123.863us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| csrng_csr_hw_reset | 1.000s | 25.381us | 1 | 1 | 100.00 | |
| csrng_csr_rw | 1.000s | 14.056us | 1 | 1 | 100.00 | |
| csrng_csr_aliasing | 1.000s | 31.575us | 1 | 1 | 100.00 | |
| csrng_same_csr_outstanding | 2.000s | 186.963us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| csrng_csr_hw_reset | 1.000s | 25.381us | 1 | 1 | 100.00 | |
| csrng_csr_rw | 1.000s | 14.056us | 1 | 1 | 100.00 | |
| csrng_csr_aliasing | 1.000s | 31.575us | 1 | 1 | 100.00 | |
| csrng_same_csr_outstanding | 2.000s | 186.963us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| csrng_sec_cm | 12.000s | 64.141us | 1 | 1 | 100.00 | |
| csrng_tl_intg_err | 69.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_regwen | 2 | 2 | 100.00 | |||
| csrng_regwen | 11.000s | 16.281us | 1 | 1 | 100.00 | |
| csrng_csr_rw | 1.000s | 14.056us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 1 | 1 | 100.00 | |||
| csrng_alert | 16.000s | 737.421us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 1 | 1 | 100.00 | |||
| csrng_stress_all | 133.000s | 13329.624us | 1 | 1 | 100.00 | |
| sec_cm_main_sm_fsm_sparse | 3 | 3 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| csrng_sec_cm | 12.000s | 64.141us | 1 | 1 | 100.00 | |
| sec_cm_cmd_stage_fsm_sparse | 3 | 3 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| csrng_sec_cm | 12.000s | 64.141us | 1 | 1 | 100.00 | |
| sec_cm_ctr_drbg_fsm_sparse | 3 | 3 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| csrng_sec_cm | 12.000s | 64.141us | 1 | 1 | 100.00 | |
| sec_cm_ctr_drbg_ctr_redun | 3 | 3 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| csrng_sec_cm | 12.000s | 64.141us | 1 | 1 | 100.00 | |
| sec_cm_gen_cmd_ctr_redun | 3 | 3 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| csrng_sec_cm | 12.000s | 64.141us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_mubi | 1 | 1 | 100.00 | |||
| csrng_alert | 16.000s | 737.421us | 1 | 1 | 100.00 | |
| sec_cm_main_sm_ctr_local_esc | 2 | 2 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| sec_cm_constants_lc_gated | 1 | 1 | 100.00 | |||
| csrng_stress_all | 133.000s | 13329.624us | 1 | 1 | 100.00 | |
| sec_cm_sw_genbits_bus_consistency | 1 | 1 | 100.00 | |||
| csrng_alert | 16.000s | 737.421us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 0 | 1 | 0.00 | |||
| csrng_tl_intg_err | 69.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_aes_cipher_fsm_sparse | 3 | 3 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| csrng_sec_cm | 12.000s | 64.141us | 1 | 1 | 100.00 | |
| sec_cm_aes_cipher_fsm_redun | 2 | 2 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| sec_cm_aes_cipher_ctrl_sparse | 2 | 2 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| sec_cm_aes_cipher_fsm_local_esc | 2 | 2 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| sec_cm_aes_cipher_ctr_redun | 3 | 3 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| csrng_sec_cm | 12.000s | 64.141us | 1 | 1 | 100.00 | |
| sec_cm_aes_cipher_data_reg_local_esc | 2 | 2 | 100.00 | |||
| csrng_intr | 14.000s | 283.975us | 1 | 1 | 100.00 | |
| csrng_err | 1.000s | 52.622us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| csrng_stress_all_with_rand_reset | 103.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 2 test runs | |||
| csrng_stress_all_with_rand_reset | 60261150037446488859067268479436400823221321311923265115085432521683049378524 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:17:06 UTC (total: 00:01:43)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| csrng_tl_intg_err | 21832102380787777178041035605469311566991689377213162525393787723405917734191 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:16:32 UTC (total: 00:01:09)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|