Simulation Results: edn/edn0

 
07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.47 %
  • code
  • 87.80 %
  • assert
  • 97.74 %
  • func
  • 40.87 %
  • line
  • 92.31 %
  • branch
  • 77.65 %
  • cond
  • 83.10 %
  • toggle
  • 98.14 %
Validation stages
V1
66.67%
V2
42.86%
V2S
25.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
edn_smoke 0.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.440s 156.596us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.470s 15.939us 1 1 100.00
csr_bit_bash 0 1 0.00
edn_csr_bit_bash 11.683s 0.000us 0 1 0.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.430s 30.100us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.610s 29.505us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.470s 15.939us 1 1 100.00
edn_csr_aliasing 0.430s 30.100us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 0 1 0.00
edn_genbits 0.000s 0.000us 0 1 0.00
csrng_commands 0 1 0.00
edn_genbits 0.000s 0.000us 0 1 0.00
genbits 0 1 0.00
edn_genbits 0.000s 0.000us 0 1 0.00
interrupts 0 1 0.00
edn_intr 0.000s 0.000us 0 1 0.00
alerts 0 1 0.00
edn_alert 0.000s 0.000us 0 1 0.00
errs 0 1 0.00
edn_err 0.000s 0.000us 0 1 0.00
disable 0 2 0.00
edn_disable 0.000s 0.000us 0 1 0.00
edn_disable_auto_req_mode 0.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
edn_stress_all 0.000s 0.000us 0 1 0.00
intr_test 1 1 100.00
edn_intr_test 0.450s 33.203us 1 1 100.00
alert_test 0 1 0.00
edn_alert_test 0.000s 0.000us 0 1 0.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.230s 569.612us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.230s 569.612us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.440s 156.596us 1 1 100.00
edn_csr_rw 0.470s 15.939us 1 1 100.00
edn_csr_aliasing 0.430s 30.100us 1 1 100.00
edn_same_csr_outstanding 0.490s 16.677us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.440s 156.596us 1 1 100.00
edn_csr_rw 0.470s 15.939us 1 1 100.00
edn_csr_aliasing 0.430s 30.100us 1 1 100.00
edn_same_csr_outstanding 0.490s 16.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
edn_tl_intg_err 0.640s 80.127us 1 1 100.00
sec_cm_config_regwen 0 1 0.00
edn_regwen 0.000s 0.000us 0 1 0.00
sec_cm_config_mubi 0 1 0.00
edn_alert 0.000s 0.000us 0 1 0.00
sec_cm_main_sm_fsm_sparse 0 1 0.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_ack_sm_fsm_sparse 0 1 0.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_fifo_ctr_redun 0 1 0.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_main_sm_ctr_local_esc 0 2 0.00
edn_alert 0.000s 0.000us 0 1 0.00
edn_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_cs_rdata_bus_consistency 0 1 0.00
edn_alert 0.000s 0.000us 0 1 0.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 0.640s 80.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job cancelled because one of its dependencies failed or was killed. 12 test runs
edn_smoke 111909854866336420962536550176025709825079487043147498056012670805483714818060 None
edn_regwen 25445967488530720859973236903924087328209241441353916427224466537377361459686 None
edn_genbits 96486393580509745768504645830634954976080503559321942636386946636254072382071 None
edn_stress_all 68421065380605646616839112970627793869291991444588129641865784597235217088710 None
edn_stress_all_with_rand_reset 33318571193404997277508003690181416336996472655357990014679071747228906973069 None
edn_intr 78575179374343525114609628233438269601043584600418503372651491118065288655123 None
edn_alert 21548380635122511334169824315934304589229539429780729797539366175193442472499 None
edn_err 8939876874463785526049574250517958332498949129608064032067476628915029459376 None
edn_disable 41093744935889375436578963564124645771600365963904455695473642316520875564612 None
edn_disable_auto_req_mode 109693789883319101581372698561353233202016089714506723058872425361022914225464 None
edn_sec_cm 44230588376410414792166087257101641207816273839639963656206370061786694767796 None
edn_alert_test 48908574548627931136641657112020775025177621702042823575984103595379510001729 None
Job returned a non-zero exit code: * 1 test run
default None None
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.158 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
edn_csr_bit_bash 22245778881210627374602849765894929577179508030024689937392607738976022680933 None
Chronologic VCS simulator copyright 1991-2025
Contains Synopsys proprietary information.
Compiler version X-2025.06-SP2-1_Full64; Runtime version X-2025.06-SP2-1_Full64; Sep 7 17:20 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255