Simulation Results: edn/edn1

 
07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 87.11 %
  • code
  • 85.15 %
  • assert
  • 96.35 %
  • func
  • 79.83 %
  • line
  • 98.41 %
  • branch
  • 94.16 %
  • cond
  • 90.62 %
  • toggle
  • 95.96 %
  • FSM
  • 46.59 %
Validation stages
V1
16.67%
V2
57.14%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.410s 128.739us 1 1 100.00
csr_hw_reset 0 1 0.00
edn_csr_hw_reset 0.000s 0.000us 0 1 0.00
csr_rw 0 1 0.00
edn_csr_rw 0.000s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
edn_csr_bit_bash 0.000s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
edn_csr_aliasing 0.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
edn_csr_mem_rw_with_rand_reset 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
edn_csr_rw 0.000s 0.000us 0 1 0.00
edn_csr_aliasing 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.550s 68.062us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.550s 68.062us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.550s 68.062us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.430s 23.887us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.580s 285.976us 1 1 100.00
errs 1 1 100.00
edn_err 0.520s 29.400us 1 1 100.00
disable 2 2 100.00
edn_disable 0.420s 22.555us 1 1 100.00
edn_disable_auto_req_mode 0.500s 87.181us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.270s 443.312us 1 1 100.00
intr_test 0 1 0.00
edn_intr_test 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
edn_alert_test 0.410s 34.298us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
edn_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
edn_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_outstanding_access 0 4 0.00
edn_csr_hw_reset 0.000s 0.000us 0 1 0.00
edn_csr_rw 0.000s 0.000us 0 1 0.00
edn_csr_aliasing 0.000s 0.000us 0 1 0.00
edn_same_csr_outstanding 0.000s 0.000us 0 1 0.00
tl_d_partial_access 0 4 0.00
edn_csr_hw_reset 0.000s 0.000us 0 1 0.00
edn_csr_rw 0.000s 0.000us 0 1 0.00
edn_csr_aliasing 0.000s 0.000us 0 1 0.00
edn_same_csr_outstanding 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
edn_sec_cm 2.060s 1750.995us 1 1 100.00
edn_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.400s 122.222us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.580s 285.976us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.060s 1750.995us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.060s 1750.995us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.060s 1750.995us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.060s 1750.995us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.580s 285.976us 1 1 100.00
edn_sec_cm 2.060s 1750.995us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.580s 285.976us 1 1 100.00
sec_cm_tile_link_bus_integrity 0 1 0.00
edn_tl_intg_err 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 30.730s 7187.644us 1 1 100.00

Error Messages

   Test seed line log context
Job cancelled because one of its dependencies failed or was killed. 9 test runs
edn_tl_errors 60131451076336342694559142432508367988157748221204213826914690035971852766956 None
edn_tl_intg_err 109811043970185681955982748228653162492273900359139828803766904453478842573881 None
edn_intr_test 33264379506504593300856940363667067187215702337143885869880811838542168096865 None
edn_csr_hw_reset 97643227163016623235588072430394990163013791230608184140185719253718564179506 None
edn_csr_rw 46092481074592036089867426201128041160034135316266430259338766614374461456668 None
edn_csr_bit_bash 86602245566153669251025114545285455381523786891177232943622854975910672627204 None
edn_csr_aliasing 34085082774398684077766940347042290316113498700997657337083886300006767601591 None
edn_same_csr_outstanding 85270735264359711761533916298736408024412213679289078807255368688912477349133 None
edn_csr_mem_rw_with_rand_reset 79478915364116239214735401184410989885821116540339021568477940102176043088695 None
Job returned a non-zero exit code: * 1 test run
cover_reg_top None None
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.116 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255