| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| hmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| hmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| hmac_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| hmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| hmac_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| hmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg | 0 | 1 | 0.00 | |||
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| back_pressure | 0 | 1 | 0.00 | |||
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| test_vectors | 0 | 6 | 0.00 | |||
| hmac_test_sha256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| burst_wr | 0 | 1 | 0.00 | |||
| hmac_burst_wr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| datapath_stress | 0 | 1 | 0.00 | |||
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| error | 0 | 1 | 0.00 | |||
| hmac_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| wipe_secret | 0 | 1 | 0.00 | |||
| hmac_wipe_secret | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| save_and_restore | 0 | 6 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_burst_wr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| fifo_empty_status_interrupt | 0 | 11 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_wipe_secret | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| wide_digest_configurable_key_length | 0 | 14 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_long_msg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_back_pressure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_datapath_stress | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_burst_wr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_error | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_wipe_secret | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_sha512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac256_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac384_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_test_hmac512_vectors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| hmac_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| hmac_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| hmac_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| hmac_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| hmac_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| hmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| hmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| hmac_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| hmac_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| hmac_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| write_config_and_secret_key_during_msg_wr | 0 | 1 | 0.00 | |||
| hmac_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_reset | 0 | 1 | 0.00 | |||
| hmac_stress_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| hmac_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 1 | 0.00 | |||
| hmac_directed | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 29 test runs | |||
| hmac_smoke | 103405239355017546104774354459100339818787740833732059071038861344325222495706 | None | ||
| hmac_long_msg | 26475886034425871081650254941082578846663103418965118112638357816904128406720 | None | ||
| hmac_stress_reset | 109041994649622446063816047841714889810611833898555996766627923965057427210553 | None | ||
| hmac_back_pressure | 70443162977364006026618353345202087832112790842924084165910822494115906778355 | None | ||
| hmac_datapath_stress | 85625620922192874907682104216877483654873066959523106756365337446539533631913 | None | ||
| hmac_burst_wr | 74139157335889659555598728072225770368878999734744126373513407468140830826915 | None | ||
| hmac_error | 42207491496033010693518117209841780902500644792190709390046915536954554193902 | None | ||
| hmac_wipe_secret | 68581143626243440642982116718336776894415529503237905469492334343116906841008 | None | ||
| hmac_test_sha256_vectors | 3409718485266504839190211400706337785060289805597333432100029259358070359461 | None | ||
| hmac_test_sha384_vectors | 33140033711326964852695011275360610077599632316419319932114025143393539806210 | None | ||
| hmac_test_sha512_vectors | 56614315249100479744620091008119234946761889029305176813185381820327132069185 | None | ||
| hmac_test_hmac256_vectors | 76707054916320819283174328073800216648475542577037765204569660287822907402308 | None | ||
| hmac_test_hmac384_vectors | 20698829225555803454519371274931335302130718934660937085763032505166492797006 | None | ||
| hmac_test_hmac512_vectors | 91414592253344736713294083356760477685954079976257699380575217566430800495429 | None | ||
| hmac_stress_all | 28324272951298931636622120524444813905818567331073663372582631518749981317752 | None | ||
| hmac_stress_all_with_rand_reset | 87282279472129651535972552224563862497907004172036203871486695003189939481690 | None | ||
| hmac_directed | 69382641652235191860099219179069402324658759868200809652294962939770194273718 | None | ||
| hmac_sec_cm | 103303042832899242408598197182339241056138635840095491442860614920647637041766 | None | ||
| hmac_tl_errors | 22026610147821190556443805293729084244869688211081788202066164599960375773617 | None | ||
| hmac_tl_intg_err | 22636731515752174024561475945462392727171287860419159337837687419425014309041 | None | ||
| hmac_intr_test | 41546882090874468107451704624141296702306730752428088825473650740167201562427 | None | ||
| hmac_alert_test | 92159329757576582436839220710284775071346485964933954963978760464318853167867 | None | ||
| hmac_csr_hw_reset | 83795705508504440672145046011381240403516858870776461294600345808858152048966 | None | ||
| hmac_csr_rw | 104278751220535038284183207748656264839593129648510856171882573638548025047730 | None | ||
| hmac_csr_bit_bash | 73608189442021160432626793623950192247718394082135036657760776567488375005881 | None | ||
| hmac_csr_aliasing | 12527757750327453782803684939135544353947400270030636719861342116981459805717 | None | ||
| hmac_same_csr_outstanding | 14138685843865637380308052235561942373290041917055993558477910164496884902987 | None | ||
| hmac_csr_mem_rw_with_rand_reset | 21088500289026412266736935183049486325375734569800085024792898593865793508070 | None | ||
| hmac | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.130 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.134 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| hmac | None | None | ||