Simulation Results

Simulation Results: i2c

07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]

Coverage statistics

Total
86.60 %

code
78.84 %

assert
97.25 %

func
83.72 %

line
96.60 %

branch
92.69 %

cond
87.41 %

toggle
74.04 %

FSM
43.45 %

Validation stages

V1		100.00%
V2		92.68%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	9.970s	6383.089us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	5.630s	5112.263us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.120s	56.286us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.130s	47.619us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.280s	2583.772us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.170s	28.183us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.170s	18.107us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.130s	47.619us	1	1	100.00
	i2c_csr_aliasing	1.170s	28.183us	1	1	100.00

38/41 passed

92.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	1.510s	360.409us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	151.590s	24817.860us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	116.580s	27482.519us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.330s	67.705us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	43.750s	4733.141us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	45.310s	3975.152us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.640s	583.447us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.880s	867.675us	1	1	100.00
	i2c_host_fifo_reset_rx	5.180s	253.805us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	33.290s	11352.665us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	6.410s	2293.909us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	0.670s	187.320us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	0.800s	769.055us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	29.670s	27976.190us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	1.480s	7138.341us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	4.800s	1015.135us	1	1	100.00
	i2c_target_intr_smoke	2.190s	2039.722us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.680s	213.697us	1	1	100.00
	i2c_target_fifo_reset_tx	0.470s	760.197us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	99.410s	47777.629us	1	1	100.00
	i2c_target_stress_rd	4.800s	1015.135us	1	1	100.00
	i2c_target_intr_stress_wr	1.080s	3782.472us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	2.820s	1408.152us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	2.460s	2992.943us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	1.820s	5240.899us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.010s	325.353us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.210s	1229.312us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.540s	520.237us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	116.580s	27482.519us	1	1	100.00
	i2c_host_perf_precise	28.240s	6020.783us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	6.410s	2293.909us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.610s	208.018us	1	1	100.00
target_mode_nack_generation				2	3	66.67
	i2c_target_nack_acqfull	1.030s	461.665us	1	1	100.00
	i2c_target_nack_acqfull_addr	0.890s	764.264us	1	1	100.00
	i2c_target_nack_txstretch	0.560s	132.762us	0	1	0.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	1.510s	970.808us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	0.770s	426.175us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.070s	17.156us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.350s	81.396us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.130s	106.749us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.130s	106.749us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.120s	56.286us	1	1	100.00
	i2c_csr_rw	1.130s	47.619us	1	1	100.00
	i2c_csr_aliasing	1.170s	28.183us	1	1	100.00
	i2c_same_csr_outstanding	0.410s	21.329us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.120s	56.286us	1	1	100.00
	i2c_csr_rw	1.130s	47.619us	1	1	100.00
	i2c_csr_aliasing	1.170s	28.183us	1	1	100.00
	i2c_same_csr_outstanding	0.410s	21.329us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.160s	552.177us	1	1	100.00
	i2c_sec_cm	0.420s	43.286us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.160s	552.177us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	0.980s	426.472us	1
target_error_intr				1
	i2c_target_unexp_stop	0.810s	243.063us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	2.490s	159.352us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1296) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	39045100945220642442984021506606923750848628162066556945263562827606596465019	90	UVM_INFO @ 426471906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	72195885519205270743425259022485570762604925274353656576935360378371598046414	89	UVM_INFO @ 159351605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_error_intr	8832280587042814034377098552393837708311371211914228041600840492189284211049	118	UVM_INFO @ 360409039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	100234897404024173242492218891595813444419502271269336749251147325403391584997	90	UVM_INFO @ 769054960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1382) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	44261632673861524405338170961202564868712062972640954421150315356584279959968	84	UVM_INFO @ 243063046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: i2c_reg_block.target_nack_count reset value:				1 test run
	i2c_target_nack_txstretch	93676148318237770252459622271827238279282585859396014631808015578378181318883	84	UVM_INFO @ 132762183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---