| V1 |
|
16.67% |
| V2 |
|
14.29% |
| V2S |
|
25.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| keymgr_dpe_smoke | 5.510s | 333.550us | 1 | 1 | 100.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| keymgr_dpe_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| keymgr_dpe_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| keymgr_dpe_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| keymgr_dpe_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| keymgr_dpe_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| keymgr_dpe_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| intr_test | 0 | 1 | 0.00 | |||
| keymgr_dpe_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_alert_test | 0.410s | 16.082us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| keymgr_dpe_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| keymgr_dpe_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| keymgr_dpe_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| keymgr_dpe_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| keymgr_dpe_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| keymgr_dpe_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| keymgr_dpe_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| keymgr_dpe_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| keymgr_dpe_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| keymgr_dpe_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| keymgr_dpe_sec_cm | 4.530s | 1738.887us | 1 | 1 | 100.00 | |
| keymgr_dpe_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error | 0 | 1 | 0.00 | |||
| keymgr_dpe_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 1 | 0.00 | |||
| keymgr_dpe_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_storage_error | 0 | 1 | 0.00 | |||
| keymgr_dpe_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadowed_reset_glitch | 0 | 1 | 0.00 | |||
| keymgr_dpe_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 4.530s | 1738.887us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 4.530s | 1738.887us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 11 test runs | |||
| keymgr_dpe_shadow_reg_errors | 101395014655792975400383217489870624361084178022787247260524878233622550679450 | None | ||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 31010912863275930033132142532952766016750513734964414960472551010269297503345 | None | ||
| keymgr_dpe_tl_errors | 32199016223224271176451668131859176486839750611371722951447658265522897649369 | None | ||
| keymgr_dpe_tl_intg_err | 107528668697811726821906756903603883619111953244586509492705817256138226484355 | None | ||
| keymgr_dpe_intr_test | 69691244593405505668981894004130569495234671521341981306909522054183290208382 | None | ||
| keymgr_dpe_csr_hw_reset | 60853089122001448385657443794164198202769202547613282523661807991318966616173 | None | ||
| keymgr_dpe_csr_rw | 108415963887384730221017067061088274306977638805364654980204119656043293795144 | None | ||
| keymgr_dpe_csr_bit_bash | 115280198909545766413624552755497677686173830575021751354376455132016029355774 | None | ||
| keymgr_dpe_csr_aliasing | 29038980917327054233511392859185330549002987975484577568548625220623330034792 | None | ||
| keymgr_dpe_same_csr_outstanding | 50953617467357341731294148192198423407593444221645148150742263111254762691955 | None | ||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 93070454163077718620980953636414346476731965061938065128640818602686730500113 | None | ||
| Job returned a non-zero exit code: * | 1 test run | |||
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.134 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
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