| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| lc_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| lc_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| state_post_trans | 0 | 1 | 0.00 | |||
| lc_ctrl_state_post_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_during_op | 0 | 1 | 0.00 | |||
| lc_ctrl_regwen_during_op | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rand_wr_claim_transition_if | 0 | 1 | 0.00 | |||
| lc_ctrl_claim_transition_if | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_prog_failure | 0 | 1 | 0.00 | |||
| lc_ctrl_prog_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_state_failure | 0 | 1 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_errors | 0 | 1 | 0.00 | |||
| lc_ctrl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| security_escalation | 0 | 7 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_prog_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_security_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_prog_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_access | 0 | 13 | 0.00 | |||
| lc_ctrl_jtag_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_state_post_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_prog_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_regwen_during_op | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_priority | 0 | 1 | 0.00 | |||
| lc_ctrl_jtag_priority | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_volatile_unlock | 0 | 1 | 0.00 | |||
| lc_ctrl_volatile_unlock_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| lc_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| lc_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| lc_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| lc_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| lc_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| lc_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_transition_config_regwen | 0 | 1 | 0.00 | |||
| lc_ctrl_regwen_during_op | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_manuf_state_sparse | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_transition_ctr_sparse | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_manuf_state_bkgn_chk | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_transition_ctr_bkgn_chk | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_state_config_sparse | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_sparse | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kmac_fsm_sparse | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_local_esc | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_global_esc | 0 | 1 | 0.00 | |||
| lc_ctrl_security_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_ctrl_flow_consistency | 0 | 2 | 0.00 | |||
| lc_ctrl_state_post_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_state_post_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_intersig_mubi | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_valid_ctrl_mubi | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_digest | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_token_digest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_mux_ctrl_redun | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_token_mux | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_valid_mux_redun | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_token_mux | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 40 test runs | |||
| lc_ctrl_smoke | 33489249449088621578971443459083428165854492748582537192995904480598662315271 | None | ||
| lc_ctrl_volatile_unlock_smoke | 52788644680793502417669738489897104523767079724010069800979115392050721674031 | None | ||
| lc_ctrl_state_failure | 22851203356963557058799399453823415284703143142340333340625122445654276415210 | None | ||
| lc_ctrl_state_post_trans | 100571316155953423098165940690306837385447433862428990129124717237672863153263 | None | ||
| lc_ctrl_prog_failure | 48044634877028846636466225872030442576846673327098695650027475519713754333190 | None | ||
| lc_ctrl_errors | 39192325840650167371030268236607507808460472557351931197356872133824525466975 | None | ||
| lc_ctrl_security_escalation | 95513622779922936590593093984801739638991783551400758114336658183561024382819 | None | ||
| lc_ctrl_regwen_during_op | 57358187527904495220616074031300585760971752606565277733778561119911692088148 | None | ||
| lc_ctrl_claim_transition_if | 14858997831434127842350475198805229978059230314008663482667397374928135330677 | None | ||
| lc_ctrl_jtag_smoke | 110956284338113687226671980135738440622371303233859960621066978016476191240743 | None | ||
| lc_ctrl_jtag_state_failure | 9182873331622211377130650981067433696501498125541406128289198356978415368415 | None | ||
| lc_ctrl_jtag_state_post_trans | 36268902237786706253716101276837591890000065057935658826136295981665675165703 | None | ||
| lc_ctrl_jtag_prog_failure | 8595347611947261175017203171719917464054162336167552820959067734271220726020 | None | ||
| lc_ctrl_jtag_errors | 29999288894721861040689272606427856437417939855583245803785963827155621001947 | None | ||
| lc_ctrl_jtag_access | 17132634056090188882436287583826672612699722796542390775964256652833745669851 | None | ||
| lc_ctrl_jtag_priority | 113436443645309074637339071799383372868321706923083327681888533377033653559863 | None | ||
| lc_ctrl_jtag_regwen_during_op | 20956777050097137403623851653829364918067805433235974979651031599918251430310 | None | ||
| lc_ctrl_jtag_csr_hw_reset | 12402905376741632405248716578236479508873715014941864758672110122735805879801 | None | ||
| lc_ctrl_jtag_csr_rw | 17515516868378998516921725800063545616590984076976960680176388876076738361975 | None | ||
| lc_ctrl_jtag_csr_bit_bash | 7711972722384811870627855838870731206068250784544398155132794310619410146940 | None | ||
| lc_ctrl_jtag_csr_aliasing | 75539687935885216204913866906309192178717301111583713862787097123657078541689 | None | ||
| lc_ctrl_jtag_same_csr_outstanding | 46435601519250396943784670325562252157332482829454969565836997635818877974863 | None | ||
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 24253132550299211976642050197476131808480039799596011095183203832292605380059 | None | ||
| lc_ctrl_jtag_alert_test | 105716462218887434412467764567401719303611130706764651978587280957462439621460 | None | ||
| lc_ctrl_sec_mubi | 111270773333842123444483039029831712623861541139698839510287600334675275705981 | None | ||
| lc_ctrl_sec_token_mux | 80125677209909856748226188354373919532153090634108992996396658840504334173158 | None | ||
| lc_ctrl_sec_token_digest | 10885430849797326110785389589738202769801051980389929488950202579600431656419 | None | ||
| lc_ctrl_stress_all | 16536352031078658113699937658487012931802898166407562554776438535990694538024 | None | ||
| lc_ctrl_stress_all_with_rand_reset | 103216493637143265270053856889941273973106830912702838080624652345362975235358 | None | ||
| lc_ctrl_sec_cm | 113548916232687329262944266482484317939619668309863864642651452773276006264772 | None | ||
| lc_ctrl_tl_errors | 90064027124370694625562066309699090359423923599772595246636372518796366017988 | None | ||
| lc_ctrl_tl_intg_err | 62722562341032470804616923437671725533007386706335985542410988090536574252185 | None | ||
| lc_ctrl_alert_test | 57978425224489700643860574926869764866731150284166866210084189141071875212541 | None | ||
| lc_ctrl_csr_hw_reset | 72383358171131190907483337092100029142012533636546988595660428162345014094805 | None | ||
| lc_ctrl_csr_rw | 97843826158786304491612613293128077418959402094336448733068024794323013247335 | None | ||
| lc_ctrl_csr_bit_bash | 1508092993234874780727249754276361698027391422350590768861726616378571003010 | None | ||
| lc_ctrl_csr_aliasing | 84617381622369917705176136320233809781466669524361467704369475391723873366246 | None | ||
| lc_ctrl_same_csr_outstanding | 100025650856865932206509112502738195415609883157448046171094816214553930599495 | None | ||
| lc_ctrl_csr_mem_rw_with_rand_reset | 59089504627637765970856028411993541963973726300201322254041726642413904450540 | None | ||
| lc_ctrl | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.131 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.149 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| lc_ctrl | None | None | ||