| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| lc_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| lc_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| state_post_trans | 0 | 1 | 0.00 | |||
| lc_ctrl_state_post_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_during_op | 0 | 1 | 0.00 | |||
| lc_ctrl_regwen_during_op | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rand_wr_claim_transition_if | 0 | 1 | 0.00 | |||
| lc_ctrl_claim_transition_if | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_prog_failure | 0 | 1 | 0.00 | |||
| lc_ctrl_prog_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_state_failure | 0 | 1 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_errors | 0 | 1 | 0.00 | |||
| lc_ctrl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| security_escalation | 0 | 7 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_prog_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_security_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_prog_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_access | 0 | 13 | 0.00 | |||
| lc_ctrl_jtag_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_state_post_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_prog_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_regwen_during_op | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| jtag_priority | 0 | 1 | 0.00 | |||
| lc_ctrl_jtag_priority | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_volatile_unlock | 0 | 1 | 0.00 | |||
| lc_ctrl_volatile_unlock_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| lc_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| lc_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| lc_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| lc_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| lc_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| lc_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_transition_config_regwen | 0 | 1 | 0.00 | |||
| lc_ctrl_regwen_during_op | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_manuf_state_sparse | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_transition_ctr_sparse | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_manuf_state_bkgn_chk | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_transition_ctr_bkgn_chk | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_state_config_sparse | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_sparse | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kmac_fsm_sparse | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_local_esc | 0 | 2 | 0.00 | |||
| lc_ctrl_state_failure | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_fsm_global_esc | 0 | 1 | 0.00 | |||
| lc_ctrl_security_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_ctrl_flow_consistency | 0 | 2 | 0.00 | |||
| lc_ctrl_state_post_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_ctrl_jtag_state_post_trans | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_intersig_mubi | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_valid_ctrl_mubi | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_digest | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_token_digest | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_mux_ctrl_redun | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_token_mux | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_valid_mux_redun | 0 | 1 | 0.00 | |||
| lc_ctrl_sec_token_mux | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| lc_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 40 test runs | |||
| lc_ctrl_smoke | 68993411124297103512730693052861951337780052224623017369876983927940589522974 | None | ||
| lc_ctrl_volatile_unlock_smoke | 60605086244034348030023987864818108389784106428580340326497102681385068480186 | None | ||
| lc_ctrl_state_failure | 51621239084223129674959089271336507230810899383934810380062478114004686058942 | None | ||
| lc_ctrl_state_post_trans | 70698539428737758269965648244080438852763272352372406423327663465194571802665 | None | ||
| lc_ctrl_prog_failure | 93574152974780011460937238634774391066839895869837261389339886762337679537121 | None | ||
| lc_ctrl_errors | 18930402689420232104376435766073899596308170928553749821099227445854870490177 | None | ||
| lc_ctrl_security_escalation | 12724180057045729600666314824401582122187251748968983091227950898223755849403 | None | ||
| lc_ctrl_regwen_during_op | 82564669006502504016584047173374835613322855135796172997665182543683720783247 | None | ||
| lc_ctrl_claim_transition_if | 21953158485774295683731279912159960160893096913310354864400629952500709684039 | None | ||
| lc_ctrl_jtag_smoke | 97783202902974680092388263115779855201056748371727491574697293790452781927022 | None | ||
| lc_ctrl_jtag_state_failure | 106190869818209224937666099012824234368001902690556391189936408188970605402218 | None | ||
| lc_ctrl_jtag_state_post_trans | 48728911568846734973435777585154057975451242930170449781285251749573083191081 | None | ||
| lc_ctrl_jtag_prog_failure | 86792012042363002712124829543078334519853733725417644784357959115779372172059 | None | ||
| lc_ctrl_jtag_errors | 8697370740465006917913612493052007334212434907340326534606243156361061130883 | None | ||
| lc_ctrl_jtag_access | 51562262861048497235970674244585306886486460994309256926224072926128839103559 | None | ||
| lc_ctrl_jtag_priority | 9943368159419774471116633575257513815302355050822703582743379797474548684736 | None | ||
| lc_ctrl_jtag_regwen_during_op | 44752726019546106245619515275299417105384651037964071520922232367379635048115 | None | ||
| lc_ctrl_jtag_csr_hw_reset | 29040438003174526838958157596731416332026215208945205766590199173474357378967 | None | ||
| lc_ctrl_jtag_csr_rw | 26512896222360959481958484815784617808340753065244223169961835024799235739987 | None | ||
| lc_ctrl_jtag_csr_bit_bash | 3985581375695315114482086478365034042313528312892713030178505363303271612401 | None | ||
| lc_ctrl_jtag_csr_aliasing | 3730732025840683209673964449648685407188101332594666472738392587962011718377 | None | ||
| lc_ctrl_jtag_same_csr_outstanding | 93718900542908857526190929692054619789496009207078020011482455426321390807650 | None | ||
| lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 59327379734111272344957496453994095444524480952749649022455774527659313104271 | None | ||
| lc_ctrl_jtag_alert_test | 91415988486694229310365869356072278025283109115171322388256574322300260313151 | None | ||
| lc_ctrl_sec_mubi | 108173095244324085225535463169283869268379505668331441018123924980722075681293 | None | ||
| lc_ctrl_sec_token_mux | 49084886784902491363783064472096018634286825692555700294408950196191992617963 | None | ||
| lc_ctrl_sec_token_digest | 31086500527993242744430565701714618642602694915409742275829667702352064128198 | None | ||
| lc_ctrl_stress_all | 8187864028511173365631164899705195634264927116006618174285334055578689128610 | None | ||
| lc_ctrl_stress_all_with_rand_reset | 49529747217959825917680373669290368674253033117247628236176848507529651315268 | None | ||
| lc_ctrl_sec_cm | 47495623960777764774956281822210329133007080569619523302729827920267736061301 | None | ||
| lc_ctrl_tl_errors | 7558686023570830733744747027936426288696273741237283904327761486325110080376 | None | ||
| lc_ctrl_tl_intg_err | 16603675557763501295980339453350623951061115684983313713338118456819530604725 | None | ||
| lc_ctrl_alert_test | 81398718508923218735504712595231123637537323542339919828710648607651272976778 | None | ||
| lc_ctrl_csr_hw_reset | 65981434221060261416389746020161252604666493822915469107017079387829611288985 | None | ||
| lc_ctrl_csr_rw | 88360431834689814305207526210398191546670289055095707532746718318365392708544 | None | ||
| lc_ctrl_csr_bit_bash | 59517303125453640925219423806476557338063900376676681389917075650207964156824 | None | ||
| lc_ctrl_csr_aliasing | 24976361189089659645014676555102856870950498986341542736981323647924624704599 | None | ||
| lc_ctrl_same_csr_outstanding | 62028388878208324368478086952683366569624648936414112797042343455088083049564 | None | ||
| lc_ctrl_csr_mem_rw_with_rand_reset | 19396672852624168515927887135995151679694921219080191027503084588052008950007 | None | ||
| lc_ctrl | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.133 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.148 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| lc_ctrl | None | None | ||