| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 0 | 1 | 0.00 | |||
| otp_ctrl_wake_up | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| smoke | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| otp_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| otp_ctrl_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| otp_ctrl_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dai_access_partition_walk | 0 | 1 | 0.00 | |||
| otp_ctrl_partition_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| init_fail | 0 | 1 | 0.00 | |||
| otp_ctrl_init_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| partition_check | 0 | 2 | 0.00 | |||
| otp_ctrl_background_chks | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_check_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_during_otp_init | 0 | 1 | 0.00 | |||
| otp_ctrl_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| partition_lock | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interface_key_check | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_key_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_interactions | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_req | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_dai_errors | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_macro_errors | 0 | 1 | 0.00 | |||
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| test_access | 0 | 1 | 0.00 | |||
| otp_ctrl_test_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| otp_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| otp_ctrl_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| otp_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| otp_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| otp_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| otp_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| otp_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 0 | 2 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_secret_mem_scramble | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_digest | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_seed_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_entropy_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_integ_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_cnsty_ctr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_lfsr_redun | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_local_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_local_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_dai_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lci_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_kdi_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_scrmbl_fsm_global_esc | 0 | 1 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_timer_fsm_global_esc | 0 | 2 | 0.00 | |||
| otp_ctrl_parallel_lc_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_data_reg_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_init_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_data_reg_bkgn_chk | 0 | 1 | 0.00 | |||
| otp_ctrl_check_fail | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_regren | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_sw_unreadable | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_part_mem_sw_unwritable | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_part_mem_sw_noaccess | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_access_ctrl_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_token_valid_ctrl_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 0 | 1 | 0.00 | |||
| otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_test_bus_lc_gated | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_test_tl_lc_gate_fsm_sparse | 0 | 1 | 0.00 | |||
| otp_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_direct_access_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_check_trigger_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_check_config_regwen | 0 | 1 | 0.00 | |||
| otp_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_macro_mem_integrity | 0 | 1 | 0.00 | |||
| otp_ctrl_macro_errs | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| otp_ctrl_low_freq_read | 0 | 1 | 0.00 | |||
| otp_ctrl_low_freq_read | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| otp_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 31 test runs | |||
| otp_ctrl_wake_up | 112088306866969061114583713984805242354389006753015405148186379438065018476765 | None | ||
| otp_ctrl_smoke | 81527721325021655614771687535622415128541571422010078276492518995672382422138 | None | ||
| otp_ctrl_partition_walk | 8344349666003525813546610006257855968187776951574219529670305244561136642773 | None | ||
| otp_ctrl_low_freq_read | 74653683251592851845343091597965642756482543482430443480539784062103544075512 | None | ||
| otp_ctrl_init_fail | 25823078546567526494648823242512141653313910339523697542279339897573786116966 | None | ||
| otp_ctrl_background_chks | 35404125974647974160838632727399984349615486721530426435774963045749267346245 | None | ||
| otp_ctrl_parallel_lc_req | 39227067412583675494020319995772193733509631191687302585041057123910117622825 | None | ||
| otp_ctrl_parallel_lc_esc | 53457178182392234969451893301282651912456769527151129592532641761042540950933 | None | ||
| otp_ctrl_dai_lock | 56103711644640424031339859629907765929810782792215037358180893283320974642807 | None | ||
| otp_ctrl_dai_errs | 111172947359058031048997022301487887410136042889955202064601104021422837843569 | None | ||
| otp_ctrl_check_fail | 27383476977129351653323681216201181578222036372712442444638089601816064409386 | None | ||
| otp_ctrl_macro_errs | 8104698020985655126701685477242478749638790564430348804111890042099491423026 | None | ||
| otp_ctrl_parallel_key_req | 15254974296296217536830409946419684238742002355911530336997426404257553301278 | None | ||
| otp_ctrl_regwen | 13182551090692336463823943669102080206130936435078218103587940472502861765612 | None | ||
| otp_ctrl_test_access | 41234180399882958120122513568042636425770594529199983091880394117810178321451 | None | ||
| otp_ctrl_stress_all_with_rand_reset | 26916942563285420005841521375117346128304250186185727075665316858651723342082 | None | ||
| otp_ctrl_stress_all | 99381849073219554713952658351731917741189613891088304789841622565712902532870 | None | ||
| otp_ctrl_sec_cm | 60240624427068798307890396508447062908450930333720801411280270873392033227842 | None | ||
| otp_ctrl_tl_errors | 110722251389760813869878245143924309968200806144494520216065878077528061011552 | None | ||
| otp_ctrl_tl_intg_err | 56377889444938197065628039055158163506775073049872833397391001538170070824476 | None | ||
| otp_ctrl_alert_test | 38312808012123384875077471750691507551976370041905678432078132820822880237321 | None | ||
| otp_ctrl_intr_test | 80336624127816381089786535380860456952241836187686086919477244226694374296423 | None | ||
| otp_ctrl_mem_walk | 3429490298832708331494811240628936592683680638331854079179327239692741290867 | None | ||
| otp_ctrl_mem_partial_access | 86548790920244469113440163454466427850649272727094102317962350275785861598019 | None | ||
| otp_ctrl_csr_hw_reset | 30916611934098443623447840770113116095414736209291374995867980301484202489265 | None | ||
| otp_ctrl_csr_rw | 53612519950640983781744824269180003529074057371495896409125497350335472279498 | None | ||
| otp_ctrl_csr_bit_bash | 41398104016078713765048026425547543540811336022425443949718650516870309461556 | None | ||
| otp_ctrl_csr_aliasing | 94418059441495933695489113180062402542898343677513545568566798672673251524508 | None | ||
| otp_ctrl_same_csr_outstanding | 113557996374732712937390794785392443338218880589884875545987561913590656227933 | None | ||
| otp_ctrl_csr_mem_rw_with_rand_reset | 66449584949491999683003362347239884589369262383560721660310777016085747434552 | None | ||
| otp_ctrl | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.149 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.150 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| otp_ctrl | None | None | ||