| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| pwrmgr_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| pwrmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| pwrmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| pwrmgr_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| pwrmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| pwrmgr_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| pwrmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wakeup | 0 | 1 | 0.00 | |||
| pwrmgr_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| control_clks | 0 | 1 | 0.00 | |||
| pwrmgr_wakeup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| aborted_low_power | 0 | 2 | 0.00 | |||
| pwrmgr_aborted_low_power | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_lowpower_invalid | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| reset | 0 | 2 | 0.00 | |||
| pwrmgr_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_reset_invalid | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| main_power_glitch_reset | 0 | 1 | 0.00 | |||
| pwrmgr_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| reset_wakeup_race | 0 | 1 | 0.00 | |||
| pwrmgr_wakeup_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| lowpower_wakeup_race | 0 | 1 | 0.00 | |||
| pwrmgr_lowpower_wakeup_race | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable_rom_integrity_check | 0 | 1 | 0.00 | |||
| pwrmgr_disable_rom_integrity_check | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| pwrmgr_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| pwrmgr_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| pwrmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| pwrmgr_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| pwrmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| pwrmgr_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| pwrmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| pwrmgr_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_rom_ctrl_intersig_mubi | 0 | 2 | 0.00 | |||
| pwrmgr_wakeup_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pwrmgr_repeat_wakeup_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_rstmgr_intersig_mubi | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_rx_clk_bkgn_chk | 0 | 1 | 0.00 | |||
| pwrmgr_esc_clk_rst_malfunc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_esc_rx_clk_local_esc | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_terminal | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_flow_global_esc | 0 | 1 | 0.00 | |||
| pwrmgr_global_esc | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_pd_rst_local_esc | 0 | 1 | 0.00 | |||
| pwrmgr_glitch | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_config_regwen | 0 | 1 | 0.00 | |||
| pwrmgr_sec_cm_ctrl_config_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_wakeup_config_regwen | 0 | 1 | 0.00 | |||
| pwrmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_reset_config_regwen | 0 | 1 | 0.00 | |||
| pwrmgr_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| escalation_timeout | 0 | 1 | 0.00 | |||
| pwrmgr_escalation_timeout | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| pwrmgr_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 30 test runs | |||
| pwrmgr_smoke | 70500785324491924418373851491301337782976664965484853367796510311320774870573 | None | ||
| pwrmgr_reset | 23585266534271023551743652843038431529215096232650352597689540102589537182699 | None | ||
| pwrmgr_lowpower_wakeup_race | 94668234771024093820792875978755371230355759287341859041640282007989005848545 | None | ||
| pwrmgr_wakeup | 2650983136613697979159632976079722229034065702659536100416908564109856863681 | None | ||
| pwrmgr_wakeup_reset | 17538504677313722641447419582004499750289225377321271597453343493384179037054 | None | ||
| pwrmgr_repeat_wakeup_reset | 15861071643338814421751583630949501670071074197837607111063078652595188709514 | None | ||
| pwrmgr_aborted_low_power | 22689327731519495606721778574147119170683861372419557854197011316922867316880 | None | ||
| pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 113949604182440274255563202850405305245012429906418659409311311297882061654497 | None | ||
| pwrmgr_sec_cm_rstmgr_intersig_mubi | 72121894752144063612182263207638606385009320185786260498461184542200753756901 | None | ||
| pwrmgr_esc_clk_rst_malfunc | 24831702118472255660092263039968261871791294418389603297688414531469820501558 | None | ||
| pwrmgr_sec_cm_ctrl_config_regwen | 12149966599825743877750381410141885426390931062551790472864786653220755432756 | None | ||
| pwrmgr_global_esc | 4256244309666940457362893183792287573223069874642588651155736053742825223153 | None | ||
| pwrmgr_escalation_timeout | 74577961056506182083090039074535921581629254010086888903529779949663593071447 | None | ||
| pwrmgr_glitch | 53602973660104823813287189496464152186728468926603082513057064368703612975930 | None | ||
| pwrmgr_disable_rom_integrity_check | 17208370257259483453991831021743005739074996345193154109787420864897339099594 | None | ||
| pwrmgr_reset_invalid | 98988181214568552380389481177333514676239819077835580744532131812142987972598 | None | ||
| pwrmgr_lowpower_invalid | 34049443375257647344630036293615309903972374521274594454816724061545845890892 | None | ||
| pwrmgr_tl_errors | 110738963110080619538480972698197963095782259481367586160623892846551068860270 | None | ||
| pwrmgr_tl_intg_err | 73484571389378405469325125485564090324023214343785631054854218533198712430426 | None | ||
| pwrmgr_sec_cm | 48173307039247021311669862109562014754598654868307068829060156853715927553530 | None | ||
| pwrmgr_stress_all_with_rand_reset | 42328755150031279429252658249582292931218617020261032622481545368350676862588 | None | ||
| pwrmgr_stress_all | 86192186289704389409225696067424651392282955173130308612505785471798317925295 | None | ||
| pwrmgr_intr_test | 68285223634920935207286741153676300758555393556930143864761276001966411986018 | None | ||
| pwrmgr_csr_hw_reset | 28967200861323572584319833553357254889749716589527348599633127172823346155868 | None | ||
| pwrmgr_csr_rw | 48776886419402867774920289789754461102868764704606118177110260131008356404580 | None | ||
| pwrmgr_csr_bit_bash | 79978567248072000011569247281164067538893914090925161176493543662670681197490 | None | ||
| pwrmgr_csr_aliasing | 76760055279347918865611530766861302592312224465109762782001166758017345025997 | None | ||
| pwrmgr_same_csr_outstanding | 114003157525665939255432422833033150310247973711096126164627403454031187521024 | None | ||
| pwrmgr_csr_mem_rw_with_rand_reset | 18513858637140716897121973038276113528708730657264892023241659106094703337446 | None | ||
| pwrmgr | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.151 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.154 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| pwrmgr | None | None | ||