Simulation Results: rom_ctrl/192kb

 
07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 92.58 %
  • code
  • 90.85 %
  • assert
  • 96.23 %
  • func
  • 90.65 %
  • line
  • 98.82 %
  • branch
  • 98.19 %
  • cond
  • 96.88 %
  • toggle
  • 93.69 %
  • FSM
  • 66.67 %
Validation stages
V1
12.50%
V2
33.33%
V2S
66.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 8.410s 1033.767us 1 1 100.00
csr_hw_reset 0 1 0.00
rom_ctrl_csr_hw_reset 0.000s 0.000us 0 1 0.00
csr_rw 0 1 0.00
rom_ctrl_csr_rw 0.000s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
rom_ctrl_csr_bit_bash 0.000s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
rom_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
rom_ctrl_csr_mem_rw_with_rand_reset 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
rom_ctrl_csr_rw 0.000s 0.000us 0 1 0.00
rom_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
mem_walk 0 1 0.00
rom_ctrl_mem_walk 0.000s 0.000us 0 1 0.00
mem_partial_access 0 1 0.00
rom_ctrl_mem_partial_access 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 7.730s 2009.454us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.050s 120.616us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.860s 2016.770us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.020s 79.729us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rom_ctrl_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rom_ctrl_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_outstanding_access 0 4 0.00
rom_ctrl_csr_hw_reset 0.000s 0.000us 0 1 0.00
rom_ctrl_csr_rw 0.000s 0.000us 0 1 0.00
rom_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
rom_ctrl_same_csr_outstanding 0.000s 0.000us 0 1 0.00
tl_d_partial_access 0 4 0.00
rom_ctrl_csr_hw_reset 0.000s 0.000us 0 1 0.00
rom_ctrl_csr_rw 0.000s 0.000us 0 1 0.00
rom_ctrl_csr_aliasing 0.000s 0.000us 0 1 0.00
rom_ctrl_same_csr_outstanding 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.550s 28867.013us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
rom_ctrl_passthru_mem_tl_intg_err 0.000s 0.000us 0 1 0.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 349.910s 290.797us 1 1 100.00
rom_ctrl_tl_intg_err 0.000s 0.000us 0 1 0.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 349.910s 290.797us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 349.910s 290.797us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.550s 28867.013us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.550s 28867.013us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.550s 28867.013us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.550s 28867.013us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.550s 28867.013us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 349.910s 290.797us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 349.910s 290.797us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 8.410s 1033.767us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 8.410s 1033.767us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 8.410s 1033.767us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
rom_ctrl_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.550s 28867.013us 1 1 100.00
rom_ctrl_kmac_err_chk 14.860s 2016.770us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.550s 28867.013us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.550s 28867.013us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 95.550s 28867.013us 1 1 100.00
sec_cm_ctrl_mem_integrity 0 1 0.00
rom_ctrl_passthru_mem_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 349.910s 290.797us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 15.370s 6333.146us 1 1 100.00

Error Messages

   Test seed line log context
Job cancelled because one of its dependencies failed or was killed. 11 test runs
rom_ctrl_passthru_mem_tl_intg_err 45927293582584313146082977468459055105070936354861668677818273627715505968859 None
rom_ctrl_tl_errors 69689537449623669852617996046179483278363411511442773186540779334975712690535 None
rom_ctrl_tl_intg_err 73036601049818431023451534695452768603953206338790107972241352917475457518668 None
rom_ctrl_mem_walk 26253741929253170142242929630011476576605284676746565775661411635506350960757 None
rom_ctrl_mem_partial_access 73717258296369923708651677069351835828398804538135462508700082235185293864834 None
rom_ctrl_csr_hw_reset 4369691544542221269694889848198540717909632096429346090858595185075077345508 None
rom_ctrl_csr_rw 13694740086125622589540713556229495152683749202186760888906421792757741513966 None
rom_ctrl_csr_bit_bash 90859004661956544582326350871222622589969836174455797385101066304223768593740 None
rom_ctrl_csr_aliasing 74013642879927807098318341532946113376477657870675369751293222213185262326204 None
rom_ctrl_same_csr_outstanding 25513801769149387693937632364190306968359338463163050363023428052995490160447 None
rom_ctrl_csr_mem_rw_with_rand_reset 10236268087932625130502697670841064028043827084715818564670858287508194305186 None
Job returned a non-zero exit code: * 1 test run
cover_reg_top None None
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
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Check your license file.
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CPU time: 1.142 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 24204011720418249902623033978120562412500388628132526712887418902382673876900 85
UVM_INFO @ 2009454280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---