Simulation Results: rstmgr

 
07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 81.02 %
  • code
  • 92.12 %
  • assert
  • 98.44 %
  • func
  • 52.49 %
  • line
  • 92.87 %
  • branch
  • 87.93 %
  • cond
  • 88.48 %
  • toggle
  • 99.20 %
Validation stages
V1
83.33%
V2
45.45%
V2S
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
rstmgr_smoke 0.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.510s 151.831us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.420s 69.581us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.810s 1255.667us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.470s 92.693us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.490s 118.906us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.420s 69.581us 1 1 100.00
rstmgr_csr_aliasing 0.470s 92.693us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 0 1 0.00
rstmgr_por_stretcher 0.000s 0.000us 0 1 0.00
sw_rst 0 1 0.00
rstmgr_sw_rst 0.000s 0.000us 0 1 0.00
sw_rst_reset_race 0 1 0.00
rstmgr_sw_rst_reset_race 0.000s 0.000us 0 1 0.00
reset_info 0 1 0.00
rstmgr_reset 0.000s 0.000us 0 1 0.00
cpu_info 0 1 0.00
rstmgr_reset 0.000s 0.000us 0 1 0.00
alert_info 0 1 0.00
rstmgr_reset 0.000s 0.000us 0 1 0.00
reset_info_capture 0 1 0.00
rstmgr_reset 0.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
rstmgr_stress_all 0.000s 0.000us 0 1 0.00
alert_test 0 1 0.00
rstmgr_alert_test 0.000s 0.000us 0 1 0.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.010s 577.656us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.010s 577.656us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.510s 151.831us 1 1 100.00
rstmgr_csr_rw 0.420s 69.581us 1 1 100.00
rstmgr_csr_aliasing 0.470s 92.693us 1 1 100.00
rstmgr_same_csr_outstanding 0.850s 265.201us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.510s 151.831us 1 1 100.00
rstmgr_csr_rw 0.420s 69.581us 1 1 100.00
rstmgr_csr_aliasing 0.470s 92.693us 1 1 100.00
rstmgr_same_csr_outstanding 0.850s 265.201us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
rstmgr_sec_cm 0.000s 0.000us 0 1 0.00
rstmgr_tl_intg_err 1.700s 952.869us 1 1 100.00
prim_count_check 0 1 0.00
rstmgr_sec_cm 0.000s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
rstmgr_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.700s 952.869us 1 1 100.00
sec_cm_scan_intersig_mubi 0 1 0.00
rstmgr_sec_cm_scan_intersig_mubi 0.000s 0.000us 0 1 0.00
sec_cm_leaf_rst_bkgn_chk 0 1 0.00
rstmgr_leaf_rst_cnsty 0.000s 0.000us 0 1 0.00
sec_cm_leaf_rst_shadow 0 1 0.00
rstmgr_leaf_rst_shadow_attack 0.000s 0.000us 0 1 0.00
sec_cm_leaf_fsm_sparse 0 1 0.00
rstmgr_sec_cm 0.000s 0.000us 0 1 0.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.420s 69.581us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.420s 69.581us 1 1 100.00

Error Messages

   Test seed line log context
Job cancelled because one of its dependencies failed or was killed. 11 test runs
rstmgr_smoke 65343321211074863704494543288927431736740513941744911065413601590825693742571 None
rstmgr_por_stretcher 51061686343440528830951210043812713276084257381642209941230546327948606629848 None
rstmgr_reset 84026856410115374574537721264043372753773801507419293541699464481097639295574 None
rstmgr_sw_rst_reset_race 96605206112177444145713111850294213882829629607220614335079004052776489631790 None
rstmgr_sw_rst 42297133769468540940913526465336071462015878326867204804663270977202142255977 None
rstmgr_sec_cm_scan_intersig_mubi 44228337022551088162397994677201127614543457867550195219070680800195428680357 None
rstmgr_leaf_rst_cnsty 100944584509431526679862564468844725850108718824457795861120507814742161193369 None
rstmgr_leaf_rst_shadow_attack 39148954663116237449028566111385039629379964256884359959063902855953708941262 None
rstmgr_stress_all 67503075590775280901127805131633201228326100687515752453972730016832004808745 None
rstmgr_sec_cm 18258031213419941935998090802056467596860162875015467506512542420815185897871 None
rstmgr_alert_test 111727023060151030949774942220723466012243615827952665476640922574021516929955 None
Job returned a non-zero exit code: * 1 test run
default None None
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.153 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255