| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 0 | 1 | 0.00 | |||
| rv_timer_random | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| rv_timer_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| rv_timer_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| rv_timer_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| rv_timer_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| rv_timer_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 0 | 1 | 0.00 | |||
| rv_timer_random_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disabled | 0 | 1 | 0.00 | |||
| rv_timer_disabled | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| cfg_update_on_fly | 0 | 1 | 0.00 | |||
| rv_timer_cfg_update_on_fly | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| no_interrupt_test | 0 | 1 | 0.00 | |||
| rv_timer_cfg_update_on_fly | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress | 0 | 1 | 0.00 | |||
| rv_timer_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| rv_timer_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| rv_timer_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| rv_timer_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| rv_timer_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| rv_timer_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| rv_timer_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| rv_timer_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rv_timer_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| rv_timer_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 0 | 1 | 0.00 | |||
| rv_timer_min | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| max_value | 0 | 1 | 0.00 | |||
| rv_timer_max | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| rv_timer_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 21 test runs | |||
| rv_timer_random | 8856702450360093920156579260735523379066990134909964416451541769552786187619 | None | ||
| rv_timer_min | 3741501036572313114641711743482954514845857162702825777003883863793415028919 | None | ||
| rv_timer_max | 68260299671025340008395932985366811595457488926049556369771450201191282342868 | None | ||
| rv_timer_disabled | 59360115228136907239359462053891563077273262214078648062540526747556547950602 | None | ||
| rv_timer_cfg_update_on_fly | 101587627925272954087573528779740799965699192919491505374297554716977679482017 | None | ||
| rv_timer_random_reset | 111141721203204609276654280200440207552137727015009821523457189895306658568931 | None | ||
| rv_timer_stress_all_with_rand_reset | 107689062792776658876603692048444344084110316333450904955621886040600692992266 | None | ||
| rv_timer_stress_all | 77295054310258107761313661545260674907053818996489182606926144280699485103514 | None | ||
| rv_timer_sec_cm | 38741003507764843923447713181355830802076196127611682701474310824809510927813 | None | ||
| rv_timer_tl_errors | 65079370126773058545884638003513467565891570120420868844230352157263548302196 | None | ||
| rv_timer_tl_intg_err | 75997164883961962406617255467908975439631060776390747453297410862378907139953 | None | ||
| rv_timer_intr_test | 12251793113413305520891600837996621160982192658607121694536057475696542753948 | None | ||
| rv_timer_alert_test | 84137358106168829108339960954652473244295329037162471265762345927678780274049 | None | ||
| rv_timer_csr_hw_reset | 68516914107483017622384041244303332906055957164697354355782318501215465167554 | None | ||
| rv_timer_csr_rw | 28717227478427937405039402184566711948072247569538222068987596673162572103584 | None | ||
| rv_timer_csr_bit_bash | 84520704039966915384029709943669380694525961916194664690431330495910297826506 | None | ||
| rv_timer_csr_aliasing | 66342018126853118317786495316530119113367002849813980145092924870801326548958 | None | ||
| rv_timer_same_csr_outstanding | 61176651119411061100588114652516741046436716449296106312499026262736169507578 | None | ||
| rv_timer_csr_mem_rw_with_rand_reset | 9832212841118243150707689258892786169316695216469456496617583988688435143931 | None | ||
| rv_timer | None | None | ||
| rv_timer | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.161 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.120 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| rv_timer | None | None | ||