Simulation Results: spi_device/1r1w

 
07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
spi_device_flash_and_tpm 0.000s 0.000us 0 1 0.00
csr_hw_reset 0 1 0.00
spi_device_csr_hw_reset 0.000s 0.000us 0 1 0.00
csr_rw 0 1 0.00
spi_device_csr_rw 0.000s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
spi_device_csr_bit_bash 0.000s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
spi_device_csr_aliasing 0.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
spi_device_csr_mem_rw_with_rand_reset 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
spi_device_csr_rw 0.000s 0.000us 0 1 0.00
spi_device_csr_aliasing 0.000s 0.000us 0 1 0.00
mem_walk 0 1 0.00
spi_device_mem_walk 0.000s 0.000us 0 1 0.00
mem_partial_access 0 1 0.00
spi_device_mem_partial_access 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 0 1 0.00
spi_device_csb_read 0.000s 0.000us 0 1 0.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.000s 0.000us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.000s 0.000us 0 1 0.00
tpm_read 0 1 0.00
spi_device_tpm_rw 0.000s 0.000us 0 1 0.00
tpm_write 0 1 0.00
spi_device_tpm_rw 0.000s 0.000us 0 1 0.00
tpm_hw_reg 0 2 0.00
spi_device_tpm_read_hw_reg 0.000s 0.000us 0 1 0.00
spi_device_tpm_sts_read 0.000s 0.000us 0 1 0.00
tpm_fully_random_case 0 1 0.00
spi_device_tpm_all 0.000s 0.000us 0 1 0.00
pass_cmd_filtering 0 2 0.00
spi_device_pass_cmd_filtering 0.000s 0.000us 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
pass_addr_translation 0 2 0.00
spi_device_pass_addr_payload_swap 0.000s 0.000us 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
pass_payload_translation 0 2 0.00
spi_device_pass_addr_payload_swap 0.000s 0.000us 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
cmd_info_slots 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
cmd_read_status 0 2 0.00
spi_device_intercept 0.000s 0.000us 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
cmd_read_jedec 0 2 0.00
spi_device_intercept 0.000s 0.000us 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
cmd_read_sfdp 0 2 0.00
spi_device_intercept 0.000s 0.000us 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
cmd_fast_read 0 2 0.00
spi_device_intercept 0.000s 0.000us 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
cmd_read_pipeline 0 2 0.00
spi_device_intercept 0.000s 0.000us 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
flash_cmd_upload 0 1 0.00
spi_device_upload 0.000s 0.000us 0 1 0.00
mailbox_command 0 1 0.00
spi_device_mailbox 0.000s 0.000us 0 1 0.00
mailbox_cross_outside_command 0 1 0.00
spi_device_mailbox 0.000s 0.000us 0 1 0.00
mailbox_cross_inside_command 0 1 0.00
spi_device_mailbox 0.000s 0.000us 0 1 0.00
cmd_read_buffer 0 2 0.00
spi_device_flash_mode 0.000s 0.000us 0 1 0.00
spi_device_read_buffer_direct 0.000s 0.000us 0 1 0.00
cmd_dummy_cycle 0 2 0.00
spi_device_mailbox 0.000s 0.000us 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
quad_spi 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
dual_spi 0 1 0.00
spi_device_flash_all 0.000s 0.000us 0 1 0.00
4b_3b_feature 0 1 0.00
spi_device_cfg_cmd 0.000s 0.000us 0 1 0.00
write_enable_disable 0 1 0.00
spi_device_cfg_cmd 0.000s 0.000us 0 1 0.00
flash_mode_ignore_cmds 0 1 0.00
spi_device_flash_mode_ignore_cmds 0.000s 0.000us 0 1 0.00
TPM_with_flash_or_passthrough_mode 0 1 0.00
spi_device_flash_and_tpm 0.000s 0.000us 0 1 0.00
tpm_and_flash_trans_with_min_inactive_time 0 1 0.00
spi_device_flash_and_tpm_min_idle 0.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
spi_device_stress_all 0.000s 0.000us 0 1 0.00
alert_test 0 1 0.00
spi_device_alert_test 0.000s 0.000us 0 1 0.00
intr_test 0 1 0.00
spi_device_intr_test 0.000s 0.000us 0 1 0.00
tl_d_oob_addr_access 0 1 0.00
spi_device_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
spi_device_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_outstanding_access 0 4 0.00
spi_device_csr_hw_reset 0.000s 0.000us 0 1 0.00
spi_device_csr_rw 0.000s 0.000us 0 1 0.00
spi_device_csr_aliasing 0.000s 0.000us 0 1 0.00
spi_device_same_csr_outstanding 0.000s 0.000us 0 1 0.00
tl_d_partial_access 0 4 0.00
spi_device_csr_hw_reset 0.000s 0.000us 0 1 0.00
spi_device_csr_rw 0.000s 0.000us 0 1 0.00
spi_device_csr_aliasing 0.000s 0.000us 0 1 0.00
spi_device_same_csr_outstanding 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
spi_device_sec_cm 0.000s 0.000us 0 1 0.00
spi_device_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
spi_device_tl_intg_err 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job cancelled because one of its dependencies failed or was killed. 34 test runs
spi_device_csb_read 39182567162833069639995234206040851321162858717158374658793488853257044032300 None
spi_device_mem_parity 114505037250966978521724846339550861023529904392024988952907568415178586628802 None
spi_device_ram_cfg 73508004460265099543849735847131875524378339629664348975532378841787948340800 None
spi_device_tpm_read_hw_reg 49486609540431056360492753734306816186438246111159816794480451627414195117178 None
spi_device_tpm_all 19645948175316343175120707063272957505275283729142866723810138171774740108151 None
spi_device_tpm_sts_read 113113638025081439282475307482541489622110121944140733128646386890042458448820 None
spi_device_tpm_rw 39850351720655763613929452808610732579733953254751537163485039635111743042604 None
spi_device_pass_cmd_filtering 94365227424997609412864119801954549509308928965584469893111908336427021827430 None
spi_device_pass_addr_payload_swap 84017275378170073927261070682939580877139303626802315552501983409072752746146 None
spi_device_intercept 46558519185302972289117236452072754422124772138920944468038941943854504045679 None
spi_device_mailbox 25498974642819033932133490767131967526802848053254408958583431174932760334970 None
spi_device_upload 28216116969972075214489071990389969712921031831310585299541466491438910337153 None
spi_device_cfg_cmd 32788104066646784431915730757539153367814478212727527648918911086423704860231 None
spi_device_flash_mode 40720560864536590615724358676696842430531015168612565525247232513566405859954 None
spi_device_flash_mode_ignore_cmds 115022816367667405194333714675247553087080075821392441713285504274425985839686 None
spi_device_read_buffer_direct 102821506536046489855167606294449785424439783792941777334132913073973646362244 None
spi_device_flash_all 48903101233997859943979779700723729869630299918769346704619420365527493850016 None
spi_device_flash_and_tpm 61315368212154139125081741105257377140142015911152426090553725472143203036298 None
spi_device_flash_and_tpm_min_idle 6141268056056385382705090374598325532488579672631667778267429094465519949418 None
spi_device_stress_all 25988293083837640110917712745344586555569526849593017532881317327880343568327 None
spi_device_sec_cm 21126969234283455693921973598655142981981202077796871070931811390334443853929 None
spi_device_tl_errors 50763438484422653831051149965503948348788670347782739207667858925672303921508 None
spi_device_tl_intg_err 67681708450526072408113602721983868040097022495930018974994977566972220528625 None
spi_device_intr_test 43805535181742007178639961602369853558578071015863154632999457139360397110420 None
spi_device_alert_test 6049284639837075390581494327733121308400498112814052984194560082325775648662 None
spi_device_mem_walk 24425789716467013796988700431404353537381104148164994700977564182417249732237 None
spi_device_mem_partial_access 103095417541433023794323809130169895459306069134388720345000768148279556190130 None
spi_device_csr_hw_reset 75422360872055975264337249502444235799197676400591719007982241154822959822802 None
spi_device_csr_rw 11522704482968712286324616426517778751619819453566251011957759503936577097515 None
spi_device_csr_bit_bash 43843312150468943929074660371048313800333023283216817913025940533290653788715 None
spi_device_csr_aliasing 77833568111292858640469544935656524191786596223699186200707914871551758368605 None
spi_device_same_csr_outstanding 36769253796705141260542199998220077740988127559514560962362555526105186663578 None
spi_device_csr_mem_rw_with_rand_reset 113522624915816443133008503024212773549351750047430619376440378996615161567657 None
spi_device None None
Job returned a non-zero exit code: * 2 test runs
default None None
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.123 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
cover_reg_top None None
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.152 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
Job cancelled because all of its dependencies failed or were killed. 1 test run
spi_device None None