Simulation Results: spi_host

 
07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.04 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 86.55 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 10.000s 701.372us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 4.000s 19.810us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 4.000s 16.719us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 5.000s 1135.680us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 4.000s 17.629us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 4.000s 98.822us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 4.000s 16.719us 1 1 100.00
spi_host_csr_aliasing 4.000s 17.629us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 4.000s 34.792us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 4.000s 19.732us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 70.313us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 5.000s 260.656us 1 1 100.00
spi_host_error_cmd 4.000s 62.419us 1 1 100.00
spi_host_event 8.000s 5546.736us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 7.000s 137.176us 1 1 100.00
speed 1 1 100.00
spi_host_speed 7.000s 137.176us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 7.000s 137.176us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 172.000s 54286.040us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 150.050us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 6.000s 37.753us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 7.000s 137.176us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 7.000s 137.176us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 10.000s 701.372us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 10.000s 701.372us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 7.000s 2092.270us 1 1 100.00
spien 1 1 100.00
spi_host_spien 40.000s 5382.674us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 48.000s 2392.894us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 4.000s 693.428us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 5.000s 260.656us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 4.000s 28.815us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 4.000s 17.332us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 5.000s 140.877us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 5.000s 140.877us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 4.000s 19.810us 1 1 100.00
spi_host_csr_rw 4.000s 16.719us 1 1 100.00
spi_host_csr_aliasing 4.000s 17.629us 1 1 100.00
spi_host_same_csr_outstanding 4.000s 22.965us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 4.000s 19.810us 1 1 100.00
spi_host_csr_rw 4.000s 16.719us 1 1 100.00
spi_host_csr_aliasing 4.000s 17.629us 1 1 100.00
spi_host_same_csr_outstanding 4.000s 22.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 4.000s 251.094us 1 1 100.00
spi_host_sec_cm 6.000s 84.562us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 4.000s 251.094us 1 1 100.00