| V1 |
|
100.00% |
| V2 |
|
80.95% |
| V2S |
|
80.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 1486.420us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 19.956us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 1.000s | 41.514us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 1.000s | 449.892us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 1.000s | 36.062us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 2.000s | 351.774us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| sram_ctrl_csr_rw | 1.000s | 41.514us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 36.062us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| sram_ctrl_mem_walk | 67.000s | 7992.953us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| sram_ctrl_mem_partial_access | 65.000s | 5045.046us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 1 | 1 | 100.00 | |||
| sram_ctrl_multiple_keys | 13.000s | 18277.645us | 1 | 1 | 100.00 | |
| stress_pipeline | 1 | 1 | 100.00 | |||
| sram_ctrl_stress_pipeline | 77.000s | 4112.505us | 1 | 1 | 100.00 | |
| bijection | 0 | 1 | 0.00 | |||
| sram_ctrl_bijection | 87.000s | 0.000us | 0 | 1 | 0.00 | |
| access_during_key_req | 0 | 1 | 0.00 | |||
| sram_ctrl_access_during_key_req | 88.000s | 0.000us | 0 | 1 | 0.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 12.000s | 6848.758us | 1 | 1 | 100.00 | |
| executable | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 6.000s | 9101.754us | 1 | 1 | 100.00 | |
| partial_access | 2 | 2 | 100.00 | |||
| sram_ctrl_partial_access | 2.000s | 671.473us | 1 | 1 | 100.00 | |
| sram_ctrl_partial_access_b2b | 96.000s | 6182.871us | 1 | 1 | 100.00 | |
| max_throughput | 3 | 3 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 3521.418us | 1 | 1 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 2.000s | 2102.648us | 1 | 1 | 100.00 | |
| sram_ctrl_throughput_w_readback | 15.000s | 1510.598us | 1 | 1 | 100.00 | |
| regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 6.000s | 5909.193us | 1 | 1 | 100.00 | |
| ram_cfg | 1 | 1 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 690.549us | 1 | 1 | 100.00 | |
| non_pow2_mem_size | 2 | 3 | 66.67 | |||
| sram_ctrl_smoke | 7.000s | 1486.420us | 1 | 1 | 100.00 | |
| sram_ctrl_partial_access | 2.000s | 671.473us | 1 | 1 | 100.00 | |
| sram_ctrl_access_during_key_req | 88.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| sram_ctrl_stress_all | 87.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| sram_ctrl_alert_test | 99.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 2.000s | 282.117us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_errors | 2.000s | 282.117us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 19.956us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 1.000s | 41.514us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 36.062us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 7.000s | 13.533us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 19.956us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 1.000s | 41.514us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 36.062us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 7.000s | 13.533us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 14.000s | 29422.671us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 414.576us | 1 | 1 | 100.00 | |
| sram_ctrl_tl_intg_err | 16.000s | 215.788us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 414.576us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_tl_intg_err | 16.000s | 215.788us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 6.000s | 5909.193us | 1 | 1 | 100.00 | |
| sec_cm_readback_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_regwen | 6.000s | 5909.193us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_regwen | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_rw | 1.000s | 41.514us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 6.000s | 9101.754us | 1 | 1 | 100.00 | |
| sec_cm_exec_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 6.000s | 9101.754us | 1 | 1 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 6.000s | 9101.754us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 12.000s | 6848.758us | 1 | 1 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 1 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3602.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_integrity | 1 | 1 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 14.000s | 29422.671us | 1 | 1 | 100.00 | |
| sec_cm_mem_readback | 0 | 1 | 0.00 | |||
| sram_ctrl_readback_err | 3602.015s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 1486.420us | 1 | 1 | 100.00 | |
| sec_cm_addr_scramble | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 1486.420us | 1 | 1 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 1 | 1 | 100.00 | |||
| sram_ctrl_executable | 6.000s | 9101.754us | 1 | 1 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 414.576us | 1 | 1 | 100.00 | |
| sec_cm_key_global_esc | 1 | 1 | 100.00 | |||
| sram_ctrl_lc_escalation | 12.000s | 6848.758us | 1 | 1 | 100.00 | |
| sec_cm_key_local_esc | 1 | 1 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 414.576us | 1 | 1 | 100.00 | |
| sec_cm_init_ctr_redun | 1 | 1 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 414.576us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| sram_ctrl_smoke | 7.000s | 1486.420us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 414.576us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 30.000s | 1795.729us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 4 test runs | |||
| sram_ctrl_bijection | 100697543980770795661704505160935714020869811935995661467284754158729516906963 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:17:01 UTC (total: 00:01:27)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| sram_ctrl_access_during_key_req | 3987967534520832256721739911123690111831373043486856733548306162932617979901 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:17:02 UTC (total: 00:01:28)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| sram_ctrl_stress_all | 98338738827368357941663458696511770439434781143099961252967829304709414795511 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:17:01 UTC (total: 00:01:27)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| sram_ctrl_alert_test | 10261404371785525421804190282466336412710391615927537413913045115380395431321 | None |
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:17:13 UTC (total: 00:01:39)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
|
|
| Job timed out after * minutes | 2 test runs | |||
| sram_ctrl_readback_err | 95994321101195769255588931330656533909641193228245925780441471803115149259311 | None | ||
| sram_ctrl_mubi_enc_err | 99002481538217792697603340754027223771910982162257080715827824409237791272484 | None | ||