Simulation Results: sram_ctrl/ret

 
07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.80 %
  • code
  • 81.75 %
  • assert
  • 97.26 %
  • func
  • 93.40 %
  • block
  • 92.19 %
  • line
  • 93.78 %
  • branch
  • 88.23 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
95.24%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 86.416us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 11.000s 96.024us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 7.000s 14.930us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 117.367us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.803us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 152.153us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 7.000s 14.930us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.803us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 3.000s 864.832us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 31.000s 176.419us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 3.000s 845.526us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 129.000s 17281.551us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 16.000s 583.347us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 879.290us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 394.285us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 6.000s 333.670us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 163.815us 1 1 100.00
sram_ctrl_partial_access_b2b 76.000s 3225.132us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 1.000s 117.260us 1 1 100.00
sram_ctrl_throughput_w_partial_write 1.000s 72.534us 1 1 100.00
sram_ctrl_throughput_w_readback 7.000s 148.973us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 775.101us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 16.000s 25.210us 1 1 100.00
non_pow2_mem_size 3 3 100.00
sram_ctrl_smoke 1.000s 86.416us 1 1 100.00
sram_ctrl_partial_access 1.000s 163.815us 1 1 100.00
sram_ctrl_access_during_key_req 12.000s 879.290us 1 1 100.00
stress_all 0 1 0.00
sram_ctrl_stress_all 58.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 22.010us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 151.431us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 151.431us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 11.000s 96.024us 1 1 100.00
sram_ctrl_csr_rw 7.000s 14.930us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.803us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 19.111us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 11.000s 96.024us 1 1 100.00
sram_ctrl_csr_rw 7.000s 14.930us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.803us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 19.111us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 7.000s 2282.387us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 694.369us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 515.819us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 694.369us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 515.819us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 775.101us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 775.101us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 7.000s 14.930us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 6.000s 333.670us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 333.670us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 6.000s 333.670us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 394.285us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3602.014s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 7.000s 2282.387us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3602.016s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 86.416us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 86.416us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 6.000s 333.670us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 694.369us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 394.285us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 694.369us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 694.369us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 86.416us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 694.369us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 23.000s 7890.282us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 101725733384028703853505885498533936497696690914103550069305882396197742715232 None
sram_ctrl_mubi_enc_err 16662438134747546145552980465938632837555162601221445194520264545105229484127 None
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
sram_ctrl_stress_all 54945274077974423065462529475094827154567768645603494184486599694669091799080 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 07, 2026 at 17:16:32 UTC (total: 00:00:58)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2