| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| sysrst_ctrl_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| input_output_inverted | 0 | 1 | 0.00 | |||
| sysrst_ctrl_in_out_inverted | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| combo_detect_ec_rst | 0 | 1 | 0.00 | |||
| sysrst_ctrl_combo_detect_ec_rst | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| combo_detect_ec_rst_with_pre_cond | 0 | 1 | 0.00 | |||
| sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| sysrst_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| sysrst_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| sysrst_ctrl_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| sysrst_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| sysrst_ctrl_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| sysrst_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sysrst_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| combo_detect | 0 | 1 | 0.00 | |||
| sysrst_ctrl_combo_detect | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| combo_detect_with_pre_cond | 0 | 1 | 0.00 | |||
| sysrst_ctrl_combo_detect_with_pre_cond | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| auto_block_key_outputs | 0 | 1 | 0.00 | |||
| sysrst_ctrl_auto_blk_key_output | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| keyboard_input_triggered_interrupt | 0 | 1 | 0.00 | |||
| sysrst_ctrl_edge_detect | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pin_output_keyboard_inversion_control | 0 | 1 | 0.00 | |||
| sysrst_ctrl_pin_override_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| pin_input_value_accessibility | 0 | 1 | 0.00 | |||
| sysrst_ctrl_pin_access_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| ec_power_on_reset | 0 | 1 | 0.00 | |||
| sysrst_ctrl_ec_pwr_on_rst | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| flash_write_protect_output | 0 | 1 | 0.00 | |||
| sysrst_ctrl_flash_wr_prot_out | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| ultra_low_power_test | 0 | 1 | 0.00 | |||
| sysrst_ctrl_ultra_low_pwr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sysrst_ctrl_feature_disable | 0 | 1 | 0.00 | |||
| sysrst_ctrl_feature_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| sysrst_ctrl_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| sysrst_ctrl_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| sysrst_ctrl_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| sysrst_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| sysrst_ctrl_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| sysrst_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sysrst_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sysrst_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sysrst_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| sysrst_ctrl_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sysrst_ctrl_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sysrst_ctrl_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sysrst_ctrl_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 0 | 2 | 0.00 | |||
| sysrst_ctrl_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sysrst_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| sysrst_ctrl_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| sysrst_ctrl_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 28 test runs | |||
| sysrst_ctrl_smoke | 83050572439446007498566495576828958344424438440945850571734173968992465110509 | None | ||
| sysrst_ctrl_in_out_inverted | 107213915447000473666550620482747958235495174863566158051044060686188154228625 | None | ||
| sysrst_ctrl_combo_detect_ec_rst | 72050322256876441929154332188521944654539939372838339921673967597800838251896 | None | ||
| sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 91920856722180748288111820368292414503717920739567658438900957965511249062932 | None | ||
| sysrst_ctrl_pin_access_test | 65137442364157244056286221206814569231465050178905712600678694930579992123919 | None | ||
| sysrst_ctrl_pin_override_test | 55338492971613341549064401332520170460523794394820751464119644789954767090116 | None | ||
| sysrst_ctrl_flash_wr_prot_out | 59567112268728359718683307947787210822269727000895813664977302880455934446053 | None | ||
| sysrst_ctrl_ec_pwr_on_rst | 88775253663308838497211712015816447655907201476687098378045155049117422966058 | None | ||
| sysrst_ctrl_auto_blk_key_output | 104668577010570638419616627779962314590623833836684295225401941742156514362765 | None | ||
| sysrst_ctrl_ultra_low_pwr | 93388446518513750788470566396398081418494102617043135584475116636964719822607 | None | ||
| sysrst_ctrl_combo_detect | 35791638387374079206165185343364359637474843992989957879568072267478578899614 | None | ||
| sysrst_ctrl_edge_detect | 109507230642608565085385753624259542263714365700635918157584302125581109657080 | None | ||
| sysrst_ctrl_combo_detect_with_pre_cond | 84040028264551530848513656988307955594123795518085937021540629179706853593267 | None | ||
| sysrst_ctrl_feature_disable | 19426767754383998719934923527170697594675960978521830359149013248601061839725 | None | ||
| sysrst_ctrl_stress_all_with_rand_reset | 21133695579882394356379384492658193449192955173093695026677278854935488966524 | None | ||
| sysrst_ctrl_stress_all | 2210540685539841135399411534201279413433119875051537490600687708598373938972 | None | ||
| sysrst_ctrl_sec_cm | 113075587534050249415139983160300116315590476906278808638774240258995813321933 | None | ||
| sysrst_ctrl_tl_errors | 96043877184954196785377375040378858001498987269893469838130069462409997655291 | None | ||
| sysrst_ctrl_tl_intg_err | 98162467970556611027881460130857191589313909219476582080332664573404880372348 | None | ||
| sysrst_ctrl_alert_test | 85420464898212772188314547769200259314869807051542932043796487702327651908310 | None | ||
| sysrst_ctrl_intr_test | 19595890154012016818131245121449722501959719832685419754608776301274227893415 | None | ||
| sysrst_ctrl_csr_hw_reset | 73927497324627327650132916060488834177140442217273715726013489289087430226131 | None | ||
| sysrst_ctrl_csr_rw | 67624847633632111854501716533265869212907614143031615217175307332282504918829 | None | ||
| sysrst_ctrl_csr_bit_bash | 91924566058504909322976624584443093139278641233759143394672867886961640815602 | None | ||
| sysrst_ctrl_csr_aliasing | 9547857025508891340556638301336402738772871217464314350771121586476577025749 | None | ||
| sysrst_ctrl_same_csr_outstanding | 39441172623695210336745982812803622884543423393706751655375111072132929161110 | None | ||
| sysrst_ctrl_csr_mem_rw_with_rand_reset | 65717187224023285226428206346796476758694116664751985679445858785691455280328 | None | ||
| sysrst_ctrl | None | None | ||
| Job returned a non-zero exit code: * | 2 test runs | |||
| default | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.143 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.145 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| sysrst_ctrl | None | None | ||