Simulation Results: uart

 
07/09/2026 17:13:53 DVSim: v1.52.1 sha: 0565e16 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 67.45 %
  • code
  • 98.12 %
  • assert
  • 96.74 %
  • func
  • 7.50 %
  • line
  • 99.21 %
  • branch
  • 97.51 %
  • cond
  • 97.42 %
  • toggle
  • 98.36 %
Validation stages
V1
83.33%
V2
27.27%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
uart_smoke 0.000s 0.000us 0 1 0.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.300s 21.810us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.320s 18.768us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.140s 83.021us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.300s 24.159us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.350s 29.771us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.320s 18.768us 1 1 100.00
uart_csr_aliasing 0.300s 24.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 0 1 0.00
uart_tx_rx 0.000s 0.000us 0 1 0.00
parity 0 2 0.00
uart_smoke 0.000s 0.000us 0 1 0.00
uart_tx_rx 0.000s 0.000us 0 1 0.00
parity_error 0 2 0.00
uart_intr 0.000s 0.000us 0 1 0.00
uart_rx_parity_err 0.000s 0.000us 0 1 0.00
watermark 0 2 0.00
uart_tx_rx 0.000s 0.000us 0 1 0.00
uart_intr 0.000s 0.000us 0 1 0.00
fifo_full 0 1 0.00
uart_fifo_full 0.000s 0.000us 0 1 0.00
fifo_overflow 0 1 0.00
uart_fifo_overflow 0.000s 0.000us 0 1 0.00
fifo_reset 0 1 0.00
uart_fifo_reset 0.000s 0.000us 0 1 0.00
rx_frame_err 0 1 0.00
uart_intr 0.000s 0.000us 0 1 0.00
rx_break_err 0 1 0.00
uart_intr 0.000s 0.000us 0 1 0.00
rx_timeout 0 1 0.00
uart_intr 0.000s 0.000us 0 1 0.00
perf 0 1 0.00
uart_perf 0.000s 0.000us 0 1 0.00
sys_loopback 0 1 0.00
uart_loopback 0.000s 0.000us 0 1 0.00
line_loopback 0 1 0.00
uart_loopback 0.000s 0.000us 0 1 0.00
rx_noise_filter 0 1 0.00
uart_noise_filter 0.000s 0.000us 0 1 0.00
rx_start_bit_filter 0 1 0.00
uart_rx_start_bit_filter 0.000s 0.000us 0 1 0.00
tx_overide 0 1 0.00
uart_tx_ovrd 0.000s 0.000us 0 1 0.00
rx_oversample 0 1 0.00
uart_rx_oversample 0.000s 0.000us 0 1 0.00
long_b2b_transfer 0 1 0.00
uart_long_xfer_wo_dly 0.000s 0.000us 0 1 0.00
stress_all 0 1 0.00
uart_stress_all 0.000s 0.000us 0 1 0.00
alert_test 0 1 0.00
uart_alert_test 0.000s 0.000us 0 1 0.00
intr_test 1 1 100.00
uart_intr_test 0.330s 18.662us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.070s 421.843us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.070s 421.843us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.300s 21.810us 1 1 100.00
uart_csr_rw 0.320s 18.768us 1 1 100.00
uart_csr_aliasing 0.300s 24.159us 1 1 100.00
uart_same_csr_outstanding 0.390s 31.338us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.300s 21.810us 1 1 100.00
uart_csr_rw 0.320s 18.768us 1 1 100.00
uart_csr_aliasing 0.300s 24.159us 1 1 100.00
uart_same_csr_outstanding 0.390s 31.338us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
uart_sec_cm 0.000s 0.000us 0 1 0.00
uart_tl_intg_err 0.470s 204.607us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.470s 204.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
uart_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job cancelled because one of its dependencies failed or was killed. 18 test runs
uart_smoke 60453165530778316547513676399659057519298568546753410166747040128189421531661 None
uart_tx_rx 103549385716067797007939711652250258692949902879087926589791063390398780981649 None
uart_fifo_full 21759838826108616817393783798020812398376697341593977615627522098435620763790 None
uart_fifo_overflow 20841492180264634888060250349630166762617981804706722712089857920322338596819 None
uart_fifo_reset 27190462742219732273126558236609748671037346552083102074943461501491482315441 None
uart_rx_oversample 42380078500476996378802887641713254845570095047650963478204954310180989950789 None
uart_intr 98982221115134193009137350530895482534175025971843533085410126777038783047313 None
uart_noise_filter 95932237712711087943214519598550266376951322373132815109434578631999433929594 None
uart_rx_start_bit_filter 2569023508290841431657220575842043497525409620853923708251472721836949923542 None
uart_rx_parity_err 101467932740642857994321129081091077637233056645152398815594640150922068297628 None
uart_tx_ovrd 99140818110432762424718397920984089182597267504202989318484938054374136959814 None
uart_loopback 84068458325042537451093089514579485713667235974132024656200297230310803229825 None
uart_perf 8502011279351189523914431020725847708261249654547135965318901834446772402600 None
uart_long_xfer_wo_dly 2142907655075916839922335163757890599929027883638481003741085784504722583562 None
uart_stress_all_with_rand_reset 7869304999029914018138880725513545586954900179314507468343264458956388024335 None
uart_stress_all 14097362332343011626108141264130041759951867912042387654452836919422835528378 None
uart_sec_cm 54914489385831488405997924112350125552473327022634903360911976706299127493705 None
uart_alert_test 38937104686714467247024687712994430042171599374227156116019342099508349679045 None
Job returned a non-zero exit code: * 1 test run
default None None
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.149 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255