Simulation Results: adc_ctrl

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 70.47 %
  • code
  • 96.16 %
  • assert
  • 96.60 %
  • func
  • 18.64 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 94.04 %
  • toggle
  • 100.00 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
84.21%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.980s 5931.306us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.080s 1347.905us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.840s 551.657us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 24.680s 26534.386us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 0.630s 536.132us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.850s 419.143us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.840s 551.657us 1 1 100.00
adc_ctrl_csr_aliasing 0.630s 536.132us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 64.175s 0.000us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 57.551s 0.000us 0 1 0.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 45.690s 54647.667us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 7.900s 17482.222us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 51.590s 53082.851us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 44.980s 48712.484us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 10.810s 38952.824us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.690s 23603.166us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.560s 5018.383us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 44.410s 44338.479us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 138.250s 138641.097us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 40.820s 87408.316us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.480s 477.549us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.750s 469.513us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 0.720s 449.145us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 0.720s 449.145us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.080s 1347.905us 1 1 100.00
adc_ctrl_csr_rw 0.840s 551.657us 1 1 100.00
adc_ctrl_csr_aliasing 0.630s 536.132us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.810s 5212.081us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.080s 1347.905us 1 1 100.00
adc_ctrl_csr_rw 0.840s 551.657us 1 1 100.00
adc_ctrl_csr_aliasing 0.630s 536.132us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.810s 5212.081us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 4.470s 4018.852us 1 1 100.00
adc_ctrl_tl_intg_err 2.620s 4225.328us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.620s 4225.328us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 2.770s 9011.577us 0 1 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
adc_ctrl_filters_polled 55927012096200567505435045226694284577320031813158822793437936353183044313780 None
Chronologic VCS simulator copyright 1991-2025
Contains Synopsys proprietary information.
Compiler version X-2025.06-SP2-1_Full64; Runtime version X-2025.06-SP2-1_Full64; Sep 8 16:52 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
adc_ctrl_filters_polled_fixed 88771889937917324055055906210308064765459655307113473775912883951420456854439 None
Chronologic VCS simulator copyright 1991-2025
Contains Synopsys proprietary information.
Compiler version X-2025.06-SP2-1_Full64; Runtime version X-2025.06-SP2-1_Full64; Sep 8 16:52 2026
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 255
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 2 test runs
adc_ctrl_clock_gating 103261532346853645674320218037982970881897967501556832835873304588240096577911 399
UVM_INFO @ 23603165673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 20814228284207396992448147022799236063246193248796674500856429115031179512946 430
UVM_INFO @ 9011577384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---