Simulation Results: aes/masked

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.06 %
  • code
  • 94.62 %
  • assert
  • 98.38 %
  • func
  • 74.19 %
  • block
  • 95.01 %
  • line
  • 95.92 %
  • branch
  • 89.02 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 287.783us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 229.661us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 191.150us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 54.291us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 6437.099us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 27.000s 53.923us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 119.605us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 54.291us 1 1 100.00
aes_csr_aliasing 27.000s 53.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 229.661us 1 1 100.00
aes_config_error 3.000s 506.702us 1 1 100.00
aes_stress 3.000s 611.521us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 229.661us 1 1 100.00
aes_config_error 3.000s 506.702us 1 1 100.00
aes_stress 3.000s 611.521us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 611.521us 1 1 100.00
aes_b2b 10.000s 259.591us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 611.521us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 229.661us 1 1 100.00
aes_config_error 3.000s 506.702us 1 1 100.00
aes_stress 3.000s 611.521us 1 1 100.00
aes_alert_reset 7.000s 197.863us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 105.556us 1 1 100.00
aes_config_error 3.000s 506.702us 1 1 100.00
aes_alert_reset 7.000s 197.863us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 8.000s 471.883us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 706.471us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 7.000s 197.863us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 611.521us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 611.521us 1 1 100.00
aes_sideload 2.000s 238.807us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 1998.634us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 34.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 7.000s 63.522us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 182.234us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 182.234us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 191.150us 1 1 100.00
aes_csr_rw 1.000s 54.291us 1 1 100.00
aes_csr_aliasing 27.000s 53.923us 1 1 100.00
aes_same_csr_outstanding 1.000s 80.594us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 191.150us 1 1 100.00
aes_csr_rw 1.000s 54.291us 1 1 100.00
aes_csr_aliasing 27.000s 53.923us 1 1 100.00
aes_same_csr_outstanding 1.000s 80.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 1.000s 166.791us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 117.939us 0 1 0.00
aes_control_fi 13.000s 264.859us 1 1 100.00
aes_cipher_fi 7.000s 122.068us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 73.873us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 73.873us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 73.873us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 73.873us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 502.209us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1021.857us 1 1 100.00
aes_tl_intg_err 1.000s 212.107us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 212.107us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 7.000s 197.863us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 73.873us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 73.873us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 229.661us 1 1 100.00
aes_stress 3.000s 611.521us 1 1 100.00
aes_alert_reset 7.000s 197.863us 1 1 100.00
aes_core_fi 2.000s 133.088us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 506.702us 1 1 100.00
aes_stress 3.000s 611.521us 1 1 100.00
aes_core_fi 2.000s 133.088us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 73.873us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 129.569us 1 1 100.00
aes_stress 3.000s 611.521us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 611.521us 1 1 100.00
aes_sideload 2.000s 238.807us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 129.569us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 129.569us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 129.569us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 129.569us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 129.569us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 611.521us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 611.521us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 117.939us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 117.939us 0 1 0.00
aes_control_fi 13.000s 264.859us 1 1 100.00
aes_cipher_fi 7.000s 122.068us 1 1 100.00
aes_ctr_fi 4.000s 64.071us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 117.939us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 117.939us 0 1 0.00
aes_control_fi 13.000s 264.859us 1 1 100.00
aes_cipher_fi 7.000s 122.068us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 7.000s 122.068us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 117.939us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 117.939us 0 1 0.00
aes_control_fi 13.000s 264.859us 1 1 100.00
aes_ctr_fi 4.000s 64.071us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 117.939us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 117.939us 0 1 0.00
aes_control_fi 13.000s 264.859us 1 1 100.00
aes_cipher_fi 7.000s 122.068us 1 1 100.00
aes_ctr_fi 4.000s 64.071us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 7.000s 197.863us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 117.939us 0 1 0.00
aes_control_fi 13.000s 264.859us 1 1 100.00
aes_cipher_fi 7.000s 122.068us 1 1 100.00
aes_ctr_fi 4.000s 64.071us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 117.939us 0 1 0.00
aes_control_fi 13.000s 264.859us 1 1 100.00
aes_cipher_fi 7.000s 122.068us 1 1 100.00
aes_ctr_fi 4.000s 64.071us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 117.939us 0 1 0.00
aes_control_fi 13.000s 264.859us 1 1 100.00
aes_ctr_fi 4.000s 64.071us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 117.939us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 117.939us 0 1 0.00
aes_control_fi 13.000s 264.859us 1 1 100.00
aes_cipher_fi 7.000s 122.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 901.678us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 81069250230410031403937313853029144583644335098479322109115009618204901796400 19553
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 4
----| Expected corrupted: 0
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
aes_stress_all 17636243708316998818527832337373325801461248547711510802858658841843501572185 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 08, 2026 at 16:52:01 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 27580705401521578845566466865958254602747052891099448479518040820800284710426 204
UVM_INFO @ 901677967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---