Simulation Results: aes/unmasked

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.52 %
  • code
  • 90.06 %
  • assert
  • 97.73 %
  • func
  • 74.76 %
  • block
  • 90.12 %
  • line
  • 91.79 %
  • branch
  • 81.56 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
85.71%
V2
88.24%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 74.419us 1 1 100.00
smoke 1 1 100.00
aes_smoke 1.000s 62.349us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 0.000s 59.447us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 66.918us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 3.000s 759.645us 1 1 100.00
csr_aliasing 0 1 0.00
aes_csr_aliasing 26.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 0.000s 75.958us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
aes_csr_rw 1.000s 66.918us 1 1 100.00
aes_csr_aliasing 26.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 1.000s 62.349us 1 1 100.00
aes_config_error 2.000s 327.969us 1 1 100.00
aes_stress 1.000s 86.531us 1 1 100.00
key_length 3 3 100.00
aes_smoke 1.000s 62.349us 1 1 100.00
aes_config_error 2.000s 327.969us 1 1 100.00
aes_stress 1.000s 86.531us 1 1 100.00
back2back 2 2 100.00
aes_stress 1.000s 86.531us 1 1 100.00
aes_b2b 1.000s 95.998us 1 1 100.00
backpressure 1 1 100.00
aes_stress 1.000s 86.531us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 1.000s 62.349us 1 1 100.00
aes_config_error 2.000s 327.969us 1 1 100.00
aes_stress 1.000s 86.531us 1 1 100.00
aes_alert_reset 2.000s 186.762us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 64.875us 1 1 100.00
aes_config_error 2.000s 327.969us 1 1 100.00
aes_alert_reset 2.000s 186.762us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 134.624us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 758.507us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 186.762us 1 1 100.00
stress 1 1 100.00
aes_stress 1.000s 86.531us 1 1 100.00
sideload 2 2 100.00
aes_stress 1.000s 86.531us 1 1 100.00
aes_sideload 2.000s 346.645us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 1.000s 119.721us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 34.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 0.000s 80.329us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 110.738us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 110.738us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
aes_csr_hw_reset 0.000s 59.447us 1 1 100.00
aes_csr_rw 1.000s 66.918us 1 1 100.00
aes_csr_aliasing 26.000s 0.000us 0 1 0.00
aes_same_csr_outstanding 2.000s 89.774us 1 1 100.00
tl_d_partial_access 3 4 75.00
aes_csr_hw_reset 0.000s 59.447us 1 1 100.00
aes_csr_rw 1.000s 66.918us 1 1 100.00
aes_csr_aliasing 26.000s 0.000us 0 1 0.00
aes_same_csr_outstanding 2.000s 89.774us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 194.586us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 2.000s 178.059us 0 1 0.00
aes_control_fi 1.000s 55.183us 1 1 100.00
aes_cipher_fi 23.000s 10014.887us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 129.663us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 129.663us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 129.663us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 129.663us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 163.688us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1021.681us 1 1 100.00
aes_tl_intg_err 1.000s 178.208us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 1.000s 178.208us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 186.762us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 129.663us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 129.663us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 1.000s 62.349us 1 1 100.00
aes_stress 1.000s 86.531us 1 1 100.00
aes_alert_reset 2.000s 186.762us 1 1 100.00
aes_core_fi 1.000s 92.847us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 327.969us 1 1 100.00
aes_stress 1.000s 86.531us 1 1 100.00
aes_core_fi 1.000s 92.847us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 129.663us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 98.315us 1 1 100.00
aes_stress 1.000s 86.531us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 1.000s 86.531us 1 1 100.00
aes_sideload 2.000s 346.645us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 98.315us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 98.315us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 98.315us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 98.315us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 98.315us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 1.000s 86.531us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 1.000s 86.531us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 178.059us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 2.000s 178.059us 0 1 0.00
aes_control_fi 1.000s 55.183us 1 1 100.00
aes_cipher_fi 23.000s 10014.887us 0 1 0.00
aes_ctr_fi 1.000s 84.532us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 178.059us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 2.000s 178.059us 0 1 0.00
aes_control_fi 1.000s 55.183us 1 1 100.00
aes_cipher_fi 23.000s 10014.887us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 23.000s 10014.887us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 178.059us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 178.059us 0 1 0.00
aes_control_fi 1.000s 55.183us 1 1 100.00
aes_ctr_fi 1.000s 84.532us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 178.059us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 2.000s 178.059us 0 1 0.00
aes_control_fi 1.000s 55.183us 1 1 100.00
aes_cipher_fi 23.000s 10014.887us 0 1 0.00
aes_ctr_fi 1.000s 84.532us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 186.762us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 2.000s 178.059us 0 1 0.00
aes_control_fi 1.000s 55.183us 1 1 100.00
aes_cipher_fi 23.000s 10014.887us 0 1 0.00
aes_ctr_fi 1.000s 84.532us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 2.000s 178.059us 0 1 0.00
aes_control_fi 1.000s 55.183us 1 1 100.00
aes_cipher_fi 23.000s 10014.887us 0 1 0.00
aes_ctr_fi 1.000s 84.532us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 178.059us 0 1 0.00
aes_control_fi 1.000s 55.183us 1 1 100.00
aes_ctr_fi 1.000s 84.532us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 178.059us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 2.000s 178.059us 0 1 0.00
aes_control_fi 1.000s 55.183us 1 1 100.00
aes_cipher_fi 23.000s 10014.887us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 4.000s 2185.849us 0 1 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
aes_stress_all 31435412014343088808492084174370065268932725403123915162459007923734489668158 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 08, 2026 at 16:52:01 UTC (total: 00:00:34)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
aes_csr_aliasing 103684818733446071633870963565471058492009860092428196742643832921046434353213 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 08, 2026 at 16:51:53 UTC (total: 00:00:26)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 1 test run
aes_fi 88606142376206834831586952728194275871908432923189867492894424678733883524279 5445
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 1 test run
aes_cipher_fi 91628319995029778345985386170818624326800362242907897876225168947506946565443 150
UVM_INFO @ 10014887387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 26919509974626384560241343678176927913810418852840864512525322516046740433782 288
UVM_INFO @ 2185849189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---