Simulation Results: aon_timer

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 95.75 %
  • code
  • 98.59 %
  • assert
  • 97.86 %
  • func
  • 90.81 %
  • line
  • 99.09 %
  • branch
  • 98.56 %
  • cond
  • 98.69 %
  • toggle
  • 98.01 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
aon_timer_smoke 0.510s 478.758us 1 1 100.00
csr_hw_reset 1 1 100.00
aon_timer_csr_hw_reset 1.040s 1234.146us 1 1 100.00
csr_rw 1 1 100.00
aon_timer_csr_rw 0.640s 435.519us 1 1 100.00
csr_bit_bash 1 1 100.00
aon_timer_csr_bit_bash 2.330s 8916.595us 1 1 100.00
csr_aliasing 1 1 100.00
aon_timer_csr_aliasing 0.580s 512.085us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aon_timer_csr_mem_rw_with_rand_reset 0.400s 331.473us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aon_timer_csr_rw 0.640s 435.519us 1 1 100.00
aon_timer_csr_aliasing 0.580s 512.085us 1 1 100.00
mem_walk 1 1 100.00
aon_timer_mem_walk 0.330s 394.544us 1 1 100.00
mem_partial_access 1 1 100.00
aon_timer_mem_partial_access 0.520s 314.069us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
prescaler 1 1 100.00
aon_timer_prescaler 19.000s 30941.026us 1 1 100.00
jump 1 1 100.00
aon_timer_jump 0.450s 719.816us 1 1 100.00
stress_all 1 1 100.00
aon_timer_stress_all 15.390s 19121.625us 1 1 100.00
alert_test 1 1 100.00
aon_timer_alert_test 0.640s 520.500us 1 1 100.00
intr_test 1 1 100.00
aon_timer_intr_test 0.350s 364.196us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aon_timer_tl_errors 0.880s 519.602us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aon_timer_tl_errors 0.880s 519.602us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aon_timer_csr_hw_reset 1.040s 1234.146us 1 1 100.00
aon_timer_csr_rw 0.640s 435.519us 1 1 100.00
aon_timer_csr_aliasing 0.580s 512.085us 1 1 100.00
aon_timer_same_csr_outstanding 0.870s 1726.232us 1 1 100.00
tl_d_partial_access 4 4 100.00
aon_timer_csr_hw_reset 1.040s 1234.146us 1 1 100.00
aon_timer_csr_rw 0.640s 435.519us 1 1 100.00
aon_timer_csr_aliasing 0.580s 512.085us 1 1 100.00
aon_timer_same_csr_outstanding 0.870s 1726.232us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
aon_timer_sec_cm 3.300s 7548.475us 0 1 0.00
aon_timer_tl_intg_err 1.290s 4132.051us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aon_timer_tl_intg_err 1.290s 4132.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_threshold 1 1 100.00
aon_timer_smoke_max_thold 0.760s 550.141us 1 1 100.00
min_threshold 1 1 100.00
aon_timer_smoke_min_thold 0.530s 485.873us 1 1 100.00
wkup_count_hi_cdc 1 1 100.00
aon_timer_wkup_count_cdc_hi 4.800s 3775.326us 1 1 100.00
custom_intr 1 1 100.00
aon_timer_custom_intr 0.620s 711.612us 1 1 100.00
alternating_on_off 1 1 100.00
aon_timer_alternating_enable_on_off 9.660s 4160.328us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
aon_timer_stress_all_with_rand_reset 4.630s 2218.461us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [aon_timer_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
aon_timer_sec_cm 20236729329508738081942767594387299969213932624816352634580203206364632843510 151
UVM_INFO @ 7548474831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---