Simulation Results: clkmgr

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 88.69 %
  • code
  • 96.82 %
  • assert
  • 90.68 %
  • func
  • 78.56 %
  • line
  • 98.69 %
  • branch
  • 98.28 %
  • cond
  • 87.76 %
  • toggle
  • 99.36 %
  • FSM
  • 100.00 %
Validation stages
V1
16.67%
V2
64.29%
V2S
66.67%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.500s 80.661us 1 1 100.00
csr_hw_reset 0 1 0.00
clkmgr_csr_hw_reset 0.000s 0.000us 0 1 0.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.000s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.000s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.000s 0.000us 0 1 0.00
clkmgr_csr_aliasing 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.460s 44.308us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.570s 57.456us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.480s 30.654us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.370s 41.184us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.500s 80.661us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 4.560s 2365.227us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 2.350s 737.514us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 4.560s 2365.227us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 18.010s 10658.866us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.430s 78.052us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
clkmgr_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
clkmgr_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_outstanding_access 0 4 0.00
clkmgr_csr_hw_reset 0.000s 0.000us 0 1 0.00
clkmgr_csr_rw 0.000s 0.000us 0 1 0.00
clkmgr_csr_aliasing 0.000s 0.000us 0 1 0.00
clkmgr_same_csr_outstanding 0.000s 0.000us 0 1 0.00
tl_d_partial_access 0 4 0.00
clkmgr_csr_hw_reset 0.000s 0.000us 0 1 0.00
clkmgr_csr_rw 0.000s 0.000us 0 1 0.00
clkmgr_csr_aliasing 0.000s 0.000us 0 1 0.00
clkmgr_same_csr_outstanding 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 1.170s 379.123us 1 1 100.00
clkmgr_tl_intg_err 0.000s 0.000us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 0.000s 0.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.000s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 4.560s 2365.227us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 2.350s 737.514us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 0.000s 0.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.600s 64.642us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.460s 46.839us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.440s 19.257us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.390s 40.785us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.520s 43.636us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.000s 0.000us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 1.170s 379.123us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.000s 0.000us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.000s 0.000us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 1.170s 379.123us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.530s 874.348us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 30.190s 3772.156us 0 1 0.00

Error Messages

   Test seed line log context
Job cancelled because one of its dependencies failed or was killed. 10 test runs
clkmgr_shadow_reg_errors 107593330080742308683751637235887299827990891937698983453482554010176065455895 None
clkmgr_shadow_reg_errors_with_csr_rw 58046372319484553887672192228744848567252025921982882553273937020815953792197 None
clkmgr_tl_errors 101226026146810239329958132131017158817085544286839395662219762463673292701103 None
clkmgr_tl_intg_err 40304924172922121906702749138275037886076214831611732671209217786847200240983 None
clkmgr_csr_hw_reset 30144735851256081763687049084637763946279332883572278562019612272785658244986 None
clkmgr_csr_rw 82192070143217807199084170961713097110541319537665171019628284716045017549451 None
clkmgr_csr_bit_bash 48675711902324414305829727935003414447414678957628399300581062751617715006683 None
clkmgr_csr_aliasing 50158079533782762943030059071503778025279091800979474500584997464626821015221 None
clkmgr_same_csr_outstanding 15853253899582256619239661431250465557903372008858166647730886829564731885794 None
clkmgr_csr_mem_rw_with_rand_reset 10494667694240448470293826318802864401345363386261020058477925916597638543121 None
Job returned a non-zero exit code: * 1 test run
cover_reg_top None None
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.096 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
Offending '(lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False))' 1 test run
clkmgr_stress_all_with_rand_reset 1190914563548941809919194834488503220948367794984156562990618985180568844031 373
UVM_ERROR @ 3772156153 ps: (clkmgr_extclk_sva_if.sv:41) [ASSERT FAILED] IoClkBypReqFall_A
UVM_INFO @ 3772156153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---