Simulation Results: csrng

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.43 %
  • code
  • 92.03 %
  • assert
  • 94.32 %
  • func
  • 75.95 %
  • block
  • 96.87 %
  • line
  • 97.74 %
  • branch
  • 92.22 %
  • toggle
  • 92.43 %
  • FSM
  • 85.71 %
Validation stages
V1
83.33%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 88.838us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 18.096us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 142.705us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 7.000s 619.160us 1 1 100.00
csr_aliasing 0 1 0.00
csrng_csr_aliasing 24.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 1.000s 28.143us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
csrng_csr_rw 2.000s 142.705us 1 1 100.00
csrng_csr_aliasing 24.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
alerts 1 1 100.00
csrng_alert 3.000s 117.736us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 58.000s 10943.077us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 58.000s 10943.077us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 34.000s 294.515us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 53.496us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 1.000s 23.508us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 195.466us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 195.466us 1 1 100.00
tl_d_outstanding_access 3 4 75.00
csrng_csr_hw_reset 1.000s 18.096us 1 1 100.00
csrng_csr_rw 2.000s 142.705us 1 1 100.00
csrng_csr_aliasing 24.000s 0.000us 0 1 0.00
csrng_same_csr_outstanding 2.000s 22.794us 1 1 100.00
tl_d_partial_access 3 4 75.00
csrng_csr_hw_reset 1.000s 18.096us 1 1 100.00
csrng_csr_rw 2.000s 142.705us 1 1 100.00
csrng_csr_aliasing 24.000s 0.000us 0 1 0.00
csrng_same_csr_outstanding 2.000s 22.794us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 434.678us 1 1 100.00
csrng_tl_intg_err 2.000s 185.032us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 116.058us 1 1 100.00
csrng_csr_rw 2.000s 142.705us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 3.000s 117.736us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 34.000s 294.515us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
csrng_sec_cm 3.000s 434.678us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
csrng_sec_cm 3.000s 434.678us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
csrng_sec_cm 3.000s 434.678us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
csrng_sec_cm 3.000s 434.678us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
csrng_sec_cm 3.000s 434.678us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 3.000s 117.736us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 34.000s 294.515us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 3.000s 117.736us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 2.000s 185.032us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
csrng_sec_cm 3.000s 434.678us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
csrng_sec_cm 3.000s 434.678us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 262.395us 1 1 100.00
csrng_err 1.000s 46.022us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 28.000s 1189.800us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 1 test run
csrng_stress_all_with_rand_reset 35341483457696929392161457081156348146927426708069745106727465552736651878802 153
UVM_INFO @ 1189799935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
csrng_csr_aliasing 1589419180915884206637050852392066466558514635647745623082629940587360102203 None
Trying to check out license...
Xcelium_Single_Core 24.00 - Failed
Xcelium_Safety_Sim 24.00 - Failed
Xcelium_Safety 24.00 - Failed
Xcelium_Multi_Core 24.00 - Failed
Xcelium_For_Partners 24.00 - Failed
xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error LMF-03005'.
TOOL: xrun(64) 24.03-s007: Exiting on Sep 08, 2026 at 16:51:50 UTC (total: 00:00:24)
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:64: simulate] Error 2