Simulation Results: edn/edn0

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 84.51 %
  • code
  • 80.79 %
  • assert
  • 94.36 %
  • func
  • 78.37 %
  • line
  • 97.34 %
  • branch
  • 90.38 %
  • cond
  • 85.03 %
  • toggle
  • 81.74 %
  • FSM
  • 49.46 %
Validation stages
V1
16.67%
V2
57.14%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.480s 203.113us 1 1 100.00
csr_hw_reset 0 1 0.00
edn_csr_hw_reset 0.000s 0.000us 0 1 0.00
csr_rw 0 1 0.00
edn_csr_rw 0.000s 0.000us 0 1 0.00
csr_bit_bash 0 1 0.00
edn_csr_bit_bash 0.000s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
edn_csr_aliasing 0.000s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
edn_csr_mem_rw_with_rand_reset 0.000s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
edn_csr_rw 0.000s 0.000us 0 1 0.00
edn_csr_aliasing 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.590s 152.003us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.590s 152.003us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.590s 152.003us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.520s 26.392us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.640s 234.091us 1 1 100.00
errs 1 1 100.00
edn_err 0.600s 45.122us 1 1 100.00
disable 2 2 100.00
edn_disable 0.470s 24.259us 1 1 100.00
edn_disable_auto_req_mode 0.580s 297.794us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.150s 157.941us 1 1 100.00
intr_test 0 1 0.00
edn_intr_test 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
edn_alert_test 0.490s 12.558us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
edn_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
edn_tl_errors 0.000s 0.000us 0 1 0.00
tl_d_outstanding_access 0 4 0.00
edn_csr_hw_reset 0.000s 0.000us 0 1 0.00
edn_csr_rw 0.000s 0.000us 0 1 0.00
edn_csr_aliasing 0.000s 0.000us 0 1 0.00
edn_same_csr_outstanding 0.000s 0.000us 0 1 0.00
tl_d_partial_access 0 4 0.00
edn_csr_hw_reset 0.000s 0.000us 0 1 0.00
edn_csr_rw 0.000s 0.000us 0 1 0.00
edn_csr_aliasing 0.000s 0.000us 0 1 0.00
edn_same_csr_outstanding 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
edn_sec_cm 2.630s 330.141us 1 1 100.00
edn_tl_intg_err 0.000s 0.000us 0 1 0.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.490s 103.962us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.640s 234.091us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.630s 330.141us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.630s 330.141us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.630s 330.141us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.630s 330.141us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.640s 234.091us 1 1 100.00
edn_sec_cm 2.630s 330.141us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.640s 234.091us 1 1 100.00
sec_cm_tile_link_bus_integrity 0 1 0.00
edn_tl_intg_err 0.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 22.650s 2355.452us 1 1 100.00

Error Messages

   Test seed line log context
Job cancelled because one of its dependencies failed or was killed. 9 test runs
edn_tl_errors 94634216690793976060881285749714172873952047136319897514146731812196479268711 None
edn_tl_intg_err 106531268261266280022209005447814700745552390946105860830552423545486072674704 None
edn_intr_test 17412595955303281409807525580498088266470190694750514245553733233304712160868 None
edn_csr_hw_reset 22318409227498859722618063151970876710411341483395462031227855107446925310604 None
edn_csr_rw 64364319519862184126488836417834827060195654213951535101414357187585460098400 None
edn_csr_bit_bash 32182416176572106916218808577021791614812262416979477554080699219013265288931 None
edn_csr_aliasing 86867367812134147085334098435485961870127636586143563278457960436141055667811 None
edn_same_csr_outstanding 7539158403558395264543770962390556940298873578422435247038480963709630916269 None
edn_csr_mem_rw_with_rand_reset 50575748978666167939867542814209406352793363401452721104107876343202177693698 None
Job returned a non-zero exit code: * 1 test run
cover_reg_top None None
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.098 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255