| V1 |
|
83.33% |
| V2 |
|
42.86% |
| V2S |
|
25.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 1 | 0.00 | |||
| edn_smoke | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| edn_csr_hw_reset | 0.460s | 27.510us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| edn_csr_rw | 0.440s | 131.869us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| edn_csr_bit_bash | 1.630s | 552.085us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| edn_csr_aliasing | 0.470s | 18.190us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| edn_csr_mem_rw_with_rand_reset | 0.560s | 103.358us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| edn_csr_rw | 0.440s | 131.869us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 0.470s | 18.190us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csrng_commands | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| genbits | 0 | 1 | 0.00 | |||
| edn_genbits | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| interrupts | 0 | 1 | 0.00 | |||
| edn_intr | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alerts | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| errs | 0 | 1 | 0.00 | |||
| edn_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| disable | 0 | 2 | 0.00 | |||
| edn_disable | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_disable_auto_req_mode | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| edn_stress_all | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| edn_intr_test | 0.470s | 15.583us | 1 | 1 | 100.00 | |
| alert_test | 0 | 1 | 0.00 | |||
| edn_alert_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| edn_tl_errors | 1.270s | 39.863us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| edn_tl_errors | 1.270s | 39.863us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| edn_csr_hw_reset | 0.460s | 27.510us | 1 | 1 | 100.00 | |
| edn_csr_rw | 0.440s | 131.869us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 0.470s | 18.190us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 0.660s | 40.896us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| edn_csr_hw_reset | 0.460s | 27.510us | 1 | 1 | 100.00 | |
| edn_csr_rw | 0.440s | 131.869us | 1 | 1 | 100.00 | |
| edn_csr_aliasing | 0.470s | 18.190us | 1 | 1 | 100.00 | |
| edn_same_csr_outstanding | 0.660s | 40.896us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 1 | 2 | 50.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_tl_intg_err | 1.140s | 196.363us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 0 | 1 | 0.00 | |||
| edn_regwen | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_config_mubi | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ack_sm_fsm_sparse | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_main_sm_ctr_local_esc | 0 | 2 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| edn_sec_cm | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_cs_rdata_bus_consistency | 0 | 1 | 0.00 | |||
| edn_alert | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| edn_tl_intg_err | 1.140s | 196.363us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| edn_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 12 test runs | |||
| edn_smoke | 63251785773757575253784368972262608074146682600175828438994949880959698016117 | None | ||
| edn_regwen | 68811297348324681176808039041534278796052908380904338274649185127704973256035 | None | ||
| edn_genbits | 102643939278859008784667286673619487672180060563190551363344940779921754216818 | None | ||
| edn_stress_all | 39183992357959053560194796490861184185919568783846185731751901463420916920351 | None | ||
| edn_stress_all_with_rand_reset | 17794180166589560759180038823107061599276167903191211426964509435893446089082 | None | ||
| edn_intr | 50241801949023121583066015911665277383905561964008476784484995868641255210307 | None | ||
| edn_alert | 36295500749191266604785290932586891220652857358313046081568864233710337908554 | None | ||
| edn_err | 65579190291778027626734268034310055284151036320399268832315170854004152345131 | None | ||
| edn_disable | 110559857702999838275270609251829256402891614634450456293912438847503919219181 | None | ||
| edn_disable_auto_req_mode | 108085677560424867478566961796444563260766630073025968699275275293174662073417 | None | ||
| edn_sec_cm | 33884320411524220027160347025499348107447084169165699209295037296976783754707 | None | ||
| edn_alert_test | 91110403783946640322692342455207558366012372837066961251441134618064849575539 | None | ||
| Job returned a non-zero exit code: * | 1 test run | |||
| default | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.106 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
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