Simulation Results: entropy_src/rng_4bits

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 76.68 %
  • code
  • 89.06 %
  • assert
  • 84.40 %
  • func
  • 56.57 %
  • block
  • 94.56 %
  • line
  • 97.21 %
  • branch
  • 86.91 %
  • toggle
  • 76.31 %
  • FSM
  • 95.83 %
Validation stages
V1
100.00%
V2
93.75%
V2S
85.71%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 24.010us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 1.000s 63.742us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 51.433us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 4.000s 2007.650us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 1.000s 33.184us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 56.170us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 51.433us 1 1 100.00
entropy_src_csr_aliasing 1.000s 33.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 2.000s 24.010us 1 1 100.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
entropy_src_fw_ov 15.000s 2789.648us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 15.000s 2789.648us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 213.000s 13023.057us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
entropy_src_intr 9.000s 3545.386us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
entropy_src_functional_alerts 8.000s 368.618us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 156.000s 14197.573us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 148.816us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 458.104us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 88.661us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 1.000s 103.707us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 8.000s 88.164us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 8.000s 88.164us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 63.742us 1 1 100.00
entropy_src_csr_rw 1.000s 51.433us 1 1 100.00
entropy_src_csr_aliasing 1.000s 33.184us 1 1 100.00
entropy_src_same_csr_outstanding 1.000s 175.178us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 1.000s 63.742us 1 1 100.00
entropy_src_csr_rw 1.000s 51.433us 1 1 100.00
entropy_src_csr_aliasing 1.000s 33.184us 1 1 100.00
entropy_src_same_csr_outstanding 1.000s 175.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 59.835us 1 1 100.00
entropy_src_tl_intg_err 3.000s 339.841us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
entropy_src_cfg_regwen 1.000s 82.790us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
entropy_src_fw_ov 15.000s 2789.648us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 148.816us 1 1 100.00
entropy_src_sec_cm 2.000s 59.835us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 148.816us 1 1 100.00
entropy_src_sec_cm 2.000s 59.835us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 38.000s 14054.405us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 148.816us 1 1 100.00
entropy_src_sec_cm 2.000s 59.835us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 148.816us 1 1 100.00
entropy_src_sec_cm 2.000s 59.835us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 148.816us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 8.000s 368.618us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 339.841us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 131.000s 13025.415us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 4.000s 1068.384us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 36178420085611994575073724977772411484095656714003159165453393056162284617176 116
UVM_INFO @ 1068383948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:269) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 1 test run
entropy_src_fw_ov 40781419554990237332592676788979649922571252944660721685330465950220231019667 424
UVM_INFO @ 2789648026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---