Simulation Results: hmac

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 75.96 %
  • code
  • 86.90 %
  • assert
  • 97.60 %
  • func
  • 43.37 %
  • line
  • 99.64 %
  • branch
  • 98.86 %
  • cond
  • 95.69 %
  • toggle
  • 46.17 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 9.860s 3513.951us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.450s 102.681us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.440s 55.017us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.550s 5650.322us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 0.600s 86.905us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.630s 58.130us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.440s 55.017us 1 1 100.00
hmac_csr_aliasing 0.600s 86.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 67.890s 76792.249us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 21.290s 964.083us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 6.220s 249.501us 1 1 100.00
hmac_test_sha384_vectors 15.320s 331.926us 1 1 100.00
hmac_test_sha512_vectors 286.960s 15971.372us 1 1 100.00
hmac_test_hmac256_vectors 6.850s 395.735us 1 1 100.00
hmac_test_hmac384_vectors 5.520s 322.900us 1 1 100.00
hmac_test_hmac512_vectors 8.480s 882.473us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 4.520s 861.903us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 425.500s 6429.151us 1 1 100.00
error 1 1 100.00
hmac_error 14.820s 2604.434us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 65.180s 23979.504us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 9.860s 3513.951us 1 1 100.00
hmac_long_msg 67.890s 76792.249us 1 1 100.00
hmac_back_pressure 21.290s 964.083us 1 1 100.00
hmac_datapath_stress 425.500s 6429.151us 1 1 100.00
hmac_burst_wr 4.520s 861.903us 1 1 100.00
hmac_stress_all 3465.360s 90727.247us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 9.860s 3513.951us 1 1 100.00
hmac_long_msg 67.890s 76792.249us 1 1 100.00
hmac_back_pressure 21.290s 964.083us 1 1 100.00
hmac_datapath_stress 425.500s 6429.151us 1 1 100.00
hmac_wipe_secret 65.180s 23979.504us 1 1 100.00
hmac_test_sha256_vectors 6.220s 249.501us 1 1 100.00
hmac_test_sha384_vectors 15.320s 331.926us 1 1 100.00
hmac_test_sha512_vectors 286.960s 15971.372us 1 1 100.00
hmac_test_hmac256_vectors 6.850s 395.735us 1 1 100.00
hmac_test_hmac384_vectors 5.520s 322.900us 1 1 100.00
hmac_test_hmac512_vectors 8.480s 882.473us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 9.860s 3513.951us 1 1 100.00
hmac_long_msg 67.890s 76792.249us 1 1 100.00
hmac_back_pressure 21.290s 964.083us 1 1 100.00
hmac_datapath_stress 425.500s 6429.151us 1 1 100.00
hmac_burst_wr 4.520s 861.903us 1 1 100.00
hmac_error 14.820s 2604.434us 1 1 100.00
hmac_wipe_secret 65.180s 23979.504us 1 1 100.00
hmac_test_sha256_vectors 6.220s 249.501us 1 1 100.00
hmac_test_sha384_vectors 15.320s 331.926us 1 1 100.00
hmac_test_sha512_vectors 286.960s 15971.372us 1 1 100.00
hmac_test_hmac256_vectors 6.850s 395.735us 1 1 100.00
hmac_test_hmac384_vectors 5.520s 322.900us 1 1 100.00
hmac_test_hmac512_vectors 8.480s 882.473us 1 1 100.00
hmac_stress_all 3465.360s 90727.247us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 3465.360s 90727.247us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.350s 11.116us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.340s 12.188us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.140s 41.859us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.140s 41.859us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.450s 102.681us 1 1 100.00
hmac_csr_rw 0.440s 55.017us 1 1 100.00
hmac_csr_aliasing 0.600s 86.905us 1 1 100.00
hmac_same_csr_outstanding 1.030s 197.514us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.450s 102.681us 1 1 100.00
hmac_csr_rw 0.440s 55.017us 1 1 100.00
hmac_csr_aliasing 0.600s 86.905us 1 1 100.00
hmac_same_csr_outstanding 1.030s 197.514us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.450s 51.204us 1 1 100.00
hmac_tl_intg_err 1.810s 177.342us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.810s 177.342us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 9.860s 3513.951us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.900s 114.283us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 78.390s 13799.489us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.670s 772.214us 1 1 100.00