Simulation Results: keymgr_dpe/earlgrey

 
08/09/2026 16:50:36 DVSim: v1.52.1 sha: 1c01039 json Branch: master Tool: vcs [X-2025.06-SP2-1_Full64]
Coverage statistics
  • Total
  • 65.10 %
  • code
  • 82.54 %
  • assert
  • 97.67 %
  • func
  • 15.09 %
  • line
  • 97.60 %
  • branch
  • 93.67 %
  • cond
  • 86.63 %
  • toggle
  • 59.12 %
  • FSM
  • 75.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_dpe_smoke 7.500s 1723.812us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 0.510s 72.003us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 0.480s 50.763us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 2.260s 253.497us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 0.540s 91.016us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 1.010s 131.142us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 0.480s 50.763us 1 1 100.00
keymgr_dpe_csr_aliasing 0.540s 91.016us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 0.400s 19.175us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 0.380s 11.513us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 0.820s 27.265us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 0.820s 27.265us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.510s 72.003us 1 1 100.00
keymgr_dpe_csr_rw 0.480s 50.763us 1 1 100.00
keymgr_dpe_csr_aliasing 0.540s 91.016us 1 1 100.00
keymgr_dpe_same_csr_outstanding 0.720s 20.390us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 0.510s 72.003us 1 1 100.00
keymgr_dpe_csr_rw 0.480s 50.763us 1 1 100.00
keymgr_dpe_csr_aliasing 0.540s 91.016us 1 1 100.00
keymgr_dpe_same_csr_outstanding 0.720s 20.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 3.350s 449.107us 1 1 100.00
keymgr_dpe_tl_intg_err 1.070s 59.696us 1 1 100.00
shadow_reg_update_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.430s 8.090us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.430s 8.090us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.430s 8.090us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
keymgr_dpe_shadow_reg_errors 0.430s 8.090us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 0.940s 129.607us 0 1 0.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 3.350s 449.107us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 3.350s 449.107us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(reg2hw.control_shadowed.slot_src_sel.q < NumInstHwSlot)' 2 test runs
keymgr_dpe_shadow_reg_errors 36301693699825579669486260803565578087499679117321759523001521960920544243709 83
UVM_ERROR @ 8090068 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 8090068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_dpe_shadow_reg_errors_with_csr_rw 28478931423400188865894596341824006087474535568357476125678510464305920601988 83
UVM_ERROR @ 129607329 ps: (keymgr_dpe.sv:320) [ASSERT FAILED] SrcSelInRange_A
UVM_INFO @ 129607329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---