| V1 |
|
12.50% |
| V2 |
|
51.72% |
| V2S |
|
25.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| kmac_smoke | 35.290s | 7255.131us | 1 | 1 | 100.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| kmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 1 | 0.00 | |||
| kmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| kmac_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| kmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| kmac_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 2 | 0.00 | |||
| kmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_walk | 0 | 1 | 0.00 | |||
| kmac_mem_walk | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| mem_partial_access | 0 | 1 | 0.00 | |||
| kmac_mem_partial_access | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg_and_output | 1 | 1 | 100.00 | |||
| kmac_long_msg_and_output | 2534.290s | 135538.064us | 1 | 1 | 100.00 | |
| burst_write | 1 | 1 | 100.00 | |||
| kmac_burst_write | 805.570s | 39992.314us | 1 | 1 | 100.00 | |
| test_vectors | 8 | 8 | 100.00 | |||
| kmac_test_vectors_sha3_224 | 26.310s | 8948.232us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_256 | 1550.980s | 463323.471us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_384 | 17.660s | 11610.667us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_512 | 11.650s | 5270.464us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_128 | 129.620s | 65448.034us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_256 | 230.410s | 76432.942us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac | 1.870s | 130.678us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac_xof | 1.350s | 121.312us | 1 | 1 | 100.00 | |
| sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 172.030s | 15610.134us | 1 | 1 | 100.00 | |
| app | 0 | 1 | 0.00 | |||
| kmac_app | 7.240s | 2260.682us | 0 | 1 | 0.00 | |
| app_with_partial_data | 0 | 1 | 0.00 | |||
| kmac_app_with_partial_data | 2.140s | 56.403us | 0 | 1 | 0.00 | |
| entropy_refresh | 0 | 1 | 0.00 | |||
| kmac_entropy_refresh | 12.340s | 3579.574us | 0 | 1 | 0.00 | |
| error | 1 | 1 | 100.00 | |||
| kmac_error | 24.980s | 691.174us | 1 | 1 | 100.00 | |
| key_error | 0 | 1 | 0.00 | |||
| kmac_key_error | 0.420s | 3.888us | 0 | 1 | 0.00 | |
| sideload_invalid | 0 | 1 | 0.00 | |||
| kmac_sideload_invalid | 0.540s | 15.151us | 0 | 1 | 0.00 | |
| edn_timeout_error | 1 | 1 | 100.00 | |||
| kmac_edn_timeout_error | 0.490s | 52.936us | 1 | 1 | 100.00 | |
| entropy_mode_error | 1 | 1 | 100.00 | |||
| kmac_entropy_mode_error | 0.730s | 52.147us | 1 | 1 | 100.00 | |
| entropy_ready_error | 0 | 1 | 0.00 | |||
| kmac_entropy_ready_error | 0.420s | 12.471us | 0 | 1 | 0.00 | |
| lc_escalation | 0 | 1 | 0.00 | |||
| kmac_lc_escalation | 0.790s | 42.931us | 0 | 1 | 0.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| kmac_stress_all | 0.620s | 9.623us | 0 | 1 | 0.00 | |
| intr_test | 0 | 1 | 0.00 | |||
| kmac_intr_test | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| kmac_alert_test | 0.450s | 44.204us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 0 | 1 | 0.00 | |||
| kmac_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_illegal_access | 0 | 1 | 0.00 | |||
| kmac_tl_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_outstanding_access | 0 | 4 | 0.00 | |||
| kmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_d_partial_access | 0 | 4 | 0.00 | |||
| kmac_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| kmac_same_csr_outstanding | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_storage_error | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadowed_reset_glitch | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors_with_csr_rw | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| tl_intg_err | 0 | 2 | 0.00 | |||
| kmac_sec_cm | 0.500s | 18.455us | 0 | 1 | 0.00 | |
| kmac_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_bus_integrity | 0 | 1 | 0.00 | |||
| kmac_tl_intg_err | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 0 | 1 | 0.00 | |||
| kmac_lc_escalation | 0.790s | 42.931us | 0 | 1 | 0.00 | |
| sec_cm_sw_key_key_masking | 1 | 1 | 100.00 | |||
| kmac_smoke | 35.290s | 7255.131us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 172.030s | 15610.134us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_shadow | 0 | 1 | 0.00 | |||
| kmac_shadow_reg_errors | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| sec_cm_fsm_sparse | 0 | 1 | 0.00 | |||
| kmac_sec_cm | 0.500s | 18.455us | 0 | 1 | 0.00 | |
| sec_cm_ctr_redun | 0 | 1 | 0.00 | |||
| kmac_sec_cm | 0.500s | 18.455us | 0 | 1 | 0.00 | |
| sec_cm_packer_ctr_redun | 0 | 1 | 0.00 | |||
| kmac_sec_cm | 0.500s | 18.455us | 0 | 1 | 0.00 | |
| sec_cm_cfg_shadowed_config_regwen | 1 | 1 | 100.00 | |||
| kmac_smoke | 35.290s | 7255.131us | 1 | 1 | 100.00 | |
| sec_cm_fsm_global_esc | 0 | 1 | 0.00 | |||
| kmac_lc_escalation | 0.790s | 42.931us | 0 | 1 | 0.00 | |
| sec_cm_fsm_local_esc | 0 | 1 | 0.00 | |||
| kmac_sec_cm | 0.500s | 18.455us | 0 | 1 | 0.00 | |
| sec_cm_absorbed_ctrl_mubi | 0 | 1 | 0.00 | |||
| kmac_mubi | 3.260s | 85.478us | 0 | 1 | 0.00 | |
| sec_cm_sw_cmd_ctrl_sparse | 1 | 1 | 100.00 | |||
| kmac_smoke | 35.290s | 7255.131us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| kmac_stress_all_with_rand_reset | 6.480s | 101.452us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 13 test runs | |||
| kmac_shadow_reg_errors | 70686941190559299491795440725541033596174588132851911198937870849645755519373 | None | ||
| kmac_shadow_reg_errors_with_csr_rw | 22470119330176873555881911879637024346103328431242370003236896914329240592389 | None | ||
| kmac_mem_walk | 114997575732119365709351725995436244846893742069467554117927995419601428435147 | None | ||
| kmac_mem_partial_access | 50706353260960390360102761309665841711343457446431780303096761160593738582823 | None | ||
| kmac_tl_errors | 22465237096494862191814424091076901386176387212002609571096501754030818942555 | None | ||
| kmac_tl_intg_err | 106815903021638203677219391401318229058038374220816354859893016864376715219441 | None | ||
| kmac_intr_test | 82973242162247450192423772011438942568352544189178848466984697416460240879747 | None | ||
| kmac_csr_hw_reset | 81552820344938539771972649859138881230050067411091544301894814787215674319218 | None | ||
| kmac_csr_rw | 87152226333221762285390092047350211167836617658612669784987588865600579968499 | None | ||
| kmac_csr_bit_bash | 109742262930057120108119246352913826637577034118212828057601630851330025792721 | None | ||
| kmac_csr_aliasing | 102925094842889784240394957766288681329553866864515761311860049540837030480885 | None | ||
| kmac_same_csr_outstanding | 106795776694133488999722455778023158449417456258893809307043158114008255037348 | None | ||
| kmac_csr_mem_rw_with_rand_reset | 45123593440153839140080191446897577183044814618269793588695527321130269542611 | None | ||
| UVM_ERROR (kmac_scoreboard.sv:524) scoreboard [scoreboard] Saw request be handled for app * when that app was not selected. | 8 test runs | |||
| kmac_app | 52128315320656372485868638023579670178962315886781655662074839950866316040616 | 81 |
UVM_INFO @ 2260682020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_app_with_partial_data | 7493722035237927794868751311654781877303959102322010977938170666618388159573 | 78 |
UVM_INFO @ 56403481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_refresh | 83797684609510452410755248994720479153890620737570389752725474087631345599201 | 84 |
UVM_INFO @ 3579574040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_mubi | 79716935096514677419384959957246002573755580886876157424949636704753592866638 | 79 |
UVM_INFO @ 85478439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_key_error | 113462019095334673533828100973987753711806800708466612806217239410022020047847 | 77 |
UVM_INFO @ 3887670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_ready_error | 75159788127547740549885600784484863711678600489561232760178853314067687666322 | 77 |
UVM_INFO @ 12470731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_stress_all | 86687490927223689308598767368840176017267562766400456649489118317256173329715 | 79 |
UVM_INFO @ 9623149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_stress_all_with_rand_reset | 91352710479882662313007626624905899359336848814899428249940234740623841393328 | 117 |
UVM_INFO @ 101451807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). | 2 test runs | |||
| kmac_lc_escalation | 105103345493526108332106169823655207033389995795690680627970014028129143913340 | 81 |
UVM_INFO @ 42930845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_sec_cm | 100762143398298656391273675574604620143944626670838981713352519669919335105995 | 79 |
UVM_INFO @ 18455341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job returned a non-zero exit code: * | 1 test run | |||
| cover_reg_top | None | None |
Please migrate to -fullopt=2024.09 or -fullopt=2025.06.
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
CPU time: 1.088 seconds to compile
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:36: do_build] Error 255
|
|
| UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] | 1 test run | |||
| kmac_sideload_invalid | 4146321297770117719893829684793138607245647297918191382832782658987975755255 | 76 |
UVM_INFO @ 15151131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|